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| author | Michael Meissner <meissner@gcc.gnu.org> | 1996-06-24 16:17:27 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 1996-06-24 16:17:27 +0000 |
| commit | 208c89cebd45aa35358b3d7307cf348390ba6c91 (patch) | |
| tree | 2167985f4f8c54451e309788a60c93f652303e5c | |
| parent | 5aae9091074b63bf1b8d4c504e7f226b45222287 (diff) | |
| download | gcc-208c89cebd45aa35358b3d7307cf348390ba6c91.zip gcc-208c89cebd45aa35358b3d7307cf348390ba6c91.tar.gz gcc-208c89cebd45aa35358b3d7307cf348390ba6c91.tar.bz2 | |
Move xor of input into insn doing int->double conversion.
From-SVN: r12324
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 27 |
1 files changed, 17 insertions, 10 deletions
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0dc5f4c..2c3f4ed 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3549,16 +3549,14 @@ (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) (use (match_dup 2)) (use (match_dup 3)) + (clobber (match_dup 4)) (clobber (reg:DF 76))])] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" " { - rtx low = gen_reg_rtx (SImode); operands[2] = force_reg (SImode, GEN_INT (0x43300000)); operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); - - emit_insn (gen_xorsi3 (low, operands[1], GEN_INT (0x80000000))); - operands[1] = low; + operands[4] = gen_reg_rtx (SImode); }") (define_insn "*floatsidf2_internal" @@ -3566,32 +3564,41 @@ (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) (use (match_operand:SI 2 "gpc_reg_operand" "r")) (use (match_operand:DF 3 "gpc_reg_operand" "f")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) (clobber (reg:DF 76))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" "#" - [(set_attr "length" "16")]) + [(set_attr "length" "20")]) (define_split [(set (match_operand:DF 0 "gpc_reg_operand" "") (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) (use (match_operand:SI 2 "gpc_reg_operand" "")) (use (match_operand:DF 3 "gpc_reg_operand" "")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "")) (clobber (reg:DF 76))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" [(set (match_dup 4) - (unspec [(match_dup 1) ;; low word + (xor:SI (match_dup 1) + (match_dup 5))) + (set (match_dup 6) + (unspec [(match_dup 4) ;; low word (reg:SI 1)] 11)) - (set (match_dup 4) + (set (match_dup 6) (unspec [(match_dup 2) ;; high word (reg:SI 1) - (match_dup 4)] 12)) + (match_dup 6)] 12)) (set (match_dup 0) - (unspec [(match_dup 4) + (unspec [(match_dup 6) (reg:SI 1)] 13)) (set (match_dup 0) (minus:DF (match_dup 0) (match_dup 3)))] - "operands[4] = gen_rtx (REG, DFmode, FPMEM_REGNUM);") + " +{ + operands[5] = GEN_INT (0x80000000); + operands[6] = gen_rtx (REG, DFmode, FPMEM_REGNUM); +}") (define_expand "floatunssidf2" [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |