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| author | Andrew Pinski <quic_apinski@quicinc.com> | 2024-06-17 16:45:34 -0700 |
|---|---|---|
| committer | Andrew Pinski <quic_apinski@quicinc.com> | 2024-06-17 16:50:00 -0700 |
| commit | 17979deb15d34dd4f036ca93d2977d0fc4d556a7 (patch) | |
| tree | 413f4fdb7e9c2047def29110ac449e4d46b721a8 | |
| parent | 67bc21af7ba35b773b5cf0e85107715f7c2240e4 (diff) | |
| download | gcc-17979deb15d34dd4f036ca93d2977d0fc4d556a7.zip gcc-17979deb15d34dd4f036ca93d2977d0fc4d556a7.tar.gz gcc-17979deb15d34dd4f036ca93d2977d0fc4d556a7.tar.bz2 | |
aarch64: Add testcase for PR97405
This aarch64 sve specific code was fixed by r15-917-gc9842f99042454
which added a riscv specific testcase so adding an aarch64 one to test
the fix does not regress is a good idea.
Committed as obvious after testing the testcase for aarch64-linux-gnu.
PR tree-optimization/97405
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/sve/pr97405-1.c: New test.
Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c new file mode 100644 index 0000000..5efa32c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr97405-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8.2-a+sve -O2" } +/* PR tree-optimization/97405 */ +#include "arm_sve.h" + +void +a (svuint8x3_t b, unsigned char *p, int c) { + if (c) + svst1_u8(svptrue_pat_b8(SV_VL16), p, svget3_u8(b, 1)); + else + svst1_u8(svwhilelt_b8(6, 6), p, svget3_u8(b, 1)); +} + |