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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-10-23 15:39:41 +0100 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-12-07 03:14:18 +0000 |
| commit | 1750c038f9d0e0e6d1ad977e7b9f69ae7cb67455 (patch) | |
| tree | 5d598186adde6cf76b1f3115dbcf88987269914c | |
| parent | df193bda748c9c3f1e23cc2c4a636db578239001 (diff) | |
| download | gcc-1750c038f9d0e0e6d1ad977e7b9f69ae7cb67455.zip gcc-1750c038f9d0e0e6d1ad977e7b9f69ae7cb67455.tar.gz gcc-1750c038f9d0e0e6d1ad977e7b9f69ae7cb67455.tar.bz2 | |
aarch64: rcpc3: Add relevant iterators to handle Neon intrinsics
The LDAP1 and STL1 Neon ACLE intrinsics, operating on 64-bit data
values, operate on single-lane (Vt.1D) or twin-lane (Vt.2D) SIMD
register configurations, either in the DI or DF modes. This leads to
the need for a mode iterator accounting for the V1DI, V1DF, V2DI and
V2DF modes.
This patch therefore introduces the new V12DIF mode iterator with
which to generate functions operating on signed 64-bit integer and
float values and V12DIUP for generating the unsigned and
polynomial-type counterparts. Along with this, we modify the
associated mode attributes accordingly in order to allow for the
implementation of the relevant backend patterns for the intrinsics.
gcc/ChangeLog:
* config/aarch64/iterators.md (V12DIF): New.
(V12DUP): Likewise.
(VEL): Add support for all V12DIF-associated modes.
(Vetype): Add support for V1DI and V1DF.
(Vel): Likewise.
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index f204850..9bbcacd 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -314,6 +314,12 @@ ;; All byte modes. (define_mode_iterator VB [V8QI V16QI]) +;; 1 and 2 lane DI and DF modes. +(define_mode_iterator V12DIF [V1DI V1DF V2DI V2DF]) + +;; 1 and 2 lane DI mode. +(define_mode_iterator V12DI [V1DI V2DI]) + ;; 2 and 4 lane SI modes. (define_mode_iterator VS [V2SI V4SI]) @@ -1324,10 +1330,10 @@ (define_mode_attr Vetype [(V8QI "b") (V16QI "b") (V4HI "h") (V8HI "h") (V2SI "s") (V4SI "s") - (V2DI "d") + (V2DI "d") (V1DI "d") (V4HF "h") (V8HF "h") (V2SF "s") (V4SF "s") - (V2DF "d") + (V2DF "d") (V1DF "d") (V2x8QI "b") (V2x4HI "h") (V2x2SI "s") (V2x1DI "d") (V2x4HF "h") (V2x2SF "s") @@ -1498,10 +1504,12 @@ (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") (V4HI "HI") (V8HI "HI") (V2SI "SI") (V4SI "SI") - (DI "DI") (V2DI "DI") + (DI "DI") (V1DI "DI") + (V2DI "DI") (V4HF "HF") (V8HF "HF") (V2SF "SF") (V4SF "SF") - (DF "DF") (V2DF "DF") + (DF "DF") (V1DF "DF") + (V2DF "DF") (SI "SI") (HI "HI") (QI "QI") (V4BF "BF") (V8BF "BF") @@ -1518,12 +1526,13 @@ (define_mode_attr Vel [(V8QI "qi") (V16QI "qi") (V4HI "hi") (V8HI "hi") (V2SI "si") (V4SI "si") - (DI "di") (V2DI "di") + (DI "di") (V1DI "si") + (V2DI "di") (V4HF "hf") (V8HF "hf") (V2SF "sf") (V4SF "sf") - (V2DF "df") (DF "df") - (SI "si") (HI "hi") - (QI "qi") + (V1DF "df") (V2DF "df") + (DF "df") (SI "si") + (HI "hi") (QI "qi") (V4BF "bf") (V8BF "bf") (VNx16QI "qi") (VNx8QI "qi") (VNx4QI "qi") (VNx2QI "qi") (VNx8HI "hi") (VNx4HI "hi") (VNx2HI "hi") |