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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-10-25 22:45:55 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@gcc.gnu.org> | 2017-10-25 22:45:55 +0000 |
| commit | 0b661358bcd72a70bbf4b903db1f0f8de98a6bbd (patch) | |
| tree | 1b167da7b2f12ecf6d7fa1c61d3c4d049f8e4f14 | |
| parent | 4273ea2378d5989dac3b8fd532eaed201e048787 (diff) | |
| download | gcc-0b661358bcd72a70bbf4b903db1f0f8de98a6bbd.zip gcc-0b661358bcd72a70bbf4b903db1f0f8de98a6bbd.tar.gz gcc-0b661358bcd72a70bbf4b903db1f0f8de98a6bbd.tar.bz2 | |
RISC-V: Add Sign/Zero extend patterns for PIC loads
Loads on RISC-V are sign-extending by default, but we weren't telling
GCC this in our PIC load patterns. This corrects the problem, and adds
a zero-extending pattern as well.
gcc/ChangeLog
2017-10-25 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
* config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
mark as a sign-extending load.
(local_pic_load_u): Define.
From-SVN: r254092
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/riscv/pic.md | 11 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 3 |
3 files changed, 19 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 796a7e8..5e297fb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-10-25 Palmer Dabbelt <palmer@dabbelt.com> + + * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. + * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s, + mark as a sign-extending load. + (local_pic_load_u): Define. + 2017-10-25 Eric Botcazou <ebotcazou@adacore.com> PR middle-end/82062 diff --git a/gcc/config/riscv/pic.md b/gcc/config/riscv/pic.md index 6a29ead..03b8f9b 100644 --- a/gcc/config/riscv/pic.md +++ b/gcc/config/riscv/pic.md @@ -22,13 +22,20 @@ ;; Simplify PIC loads to static variables. ;; These should go away once we figure out how to emit auipc discretely. -(define_insn "*local_pic_load<mode>" +(define_insn "*local_pic_load_s<mode>" [(set (match_operand:ANYI 0 "register_operand" "=r") - (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))] + (sign_extend:ANYI (mem:ANYI (match_operand 1 "absolute_symbolic_operand" ""))))] "USE_LOAD_ADDRESS_MACRO (operands[1])" "<load>\t%0,%1" [(set (attr "length") (const_int 8))]) +(define_insn "*local_pic_load_u<mode>" + [(set (match_operand:ZERO_EXTEND_LOAD 0 "register_operand" "=r") + (zero_extend:ZERO_EXTEND_LOAD (mem:ZERO_EXTEND_LOAD (match_operand 1 "absolute_symbolic_operand" ""))))] + "USE_LOAD_ADDRESS_MACRO (operands[1])" + "<load>u\t%0,%1" + [(set (attr "length") (const_int 8))]) + (define_insn "*local_pic_load<mode>" [(set (match_operand:ANYF 0 "register_operand" "=f") (mem:ANYF (match_operand 1 "absolute_symbolic_operand" ""))) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index fd9236c..9f056bb 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -259,6 +259,9 @@ ;; Iterator for QImode extension patterns. (define_mode_iterator SUPERQI [HI SI (DI "TARGET_64BIT")]) +;; Iterator for extending loads. +(define_mode_iterator ZERO_EXTEND_LOAD [QI HI (SI "TARGET_64BIT")]) + ;; Iterator for hardware integer modes narrower than XLEN. (define_mode_iterator SUBX [QI HI (SI "TARGET_64BIT")]) |