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| author | Julia Koval <julia.koval@intel.com> | 2018-03-16 09:11:27 +0100 |
|---|---|---|
| committer | Julia Koval <jkoval@gcc.gnu.org> | 2018-03-16 09:11:27 +0100 |
| commit | 057f9d20f193e883b8c4714c4444cd9513d0c187 (patch) | |
| tree | 8a40a17977cbbf13bd9b3e994d886578c066f43c | |
| parent | 7b9be7003d3272d2faac9f39a5a6835d583307e0 (diff) | |
| download | gcc-057f9d20f193e883b8c4714c4444cd9513d0c187.zip gcc-057f9d20f193e883b8c4714c4444cd9513d0c187.tar.gz gcc-057f9d20f193e883b8c4714c4444cd9513d0c187.tar.bz2 | |
Fix documentation for CLWB ISA.
gcc/
* doc/invoke.texi (Skylake Server): Add CLWB.
Cannonlake): Remove CLWB.
From-SVN: r258587
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 57e92ac..9ed1172 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-03-16 Julia Koval <julia.koval@intel.com> + + * doc/invoke.texi (Skylake Server): Add CLWB. + Cannonlake): Remove CLWB. + 2018-03-16 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/84841 diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 8354d47..aca9c8d 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -26550,14 +26550,14 @@ AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support. Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, -AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support. +CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support. @item cannonlake Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI, -AVX512IFMA, SHA, CLWB and UMIP instruction set support. +AVX512IFMA, SHA and UMIP instruction set support. @item icelake-client Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, |