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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-06-26 06:59:26 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-06-26 06:59:26 -0600 |
| commit | 03a3dffa43145f80548d32b266b9b87be07b52ee (patch) | |
| tree | 5c3b459fc9a589298cfa9f01fa3e39fc0e17ed94 | |
| parent | f80db5495d5f8455b3003951727eb6c8dc67d81d (diff) | |
| download | gcc-03a3dffa43145f80548d32b266b9b87be07b52ee.zip gcc-03a3dffa43145f80548d32b266b9b87be07b52ee.tar.gz gcc-03a3dffa43145f80548d32b266b9b87be07b52ee.tar.bz2 | |
[committed][RISC-V] Fix expected output for thead store pair test
Surya's patch to IRA has improved the code we generate for one of the thead
store pair tests for both rv32 and rv64. This patch adjusts the expectations
of that test.
I've verified that the test now passes on rv32 and rv64 in my tester. Pushing
to the trunk.
gcc/testsuite
* gcc.target/riscv/xtheadmempair-3.c: Update expected output.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c b/gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c index 5dec702..99a6ae7 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c @@ -17,13 +17,11 @@ void bar (xlen_t, xlen_t, xlen_t, xlen_t, xlen_t, xlen_t, xlen_t, xlen_t); void baz (xlen_t a, xlen_t b, xlen_t c, xlen_t d, xlen_t e, xlen_t f, xlen_t g, xlen_t h) { foo (a, b, c, d, e, f, g, h); - /* RV64: We don't use 0(sp), therefore we can only get 3 mempairs. */ - /* RV32: We don't use 0(sp)-8(sp), therefore we can only get 2 mempairs. */ bar (a, b, c, d, e, f, g, h); } -/* { dg-final { scan-assembler-times "th.ldd\t" 3 { target { rv64 } } } } */ -/* { dg-final { scan-assembler-times "th.sdd\t" 3 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.ldd\t" 4 { target { rv64 } } } } */ +/* { dg-final { scan-assembler-times "th.sdd\t" 4 { target { rv64 } } } } */ -/* { dg-final { scan-assembler-times "th.lwd\t" 2 { target { rv32 } } } } */ -/* { dg-final { scan-assembler-times "th.swd\t" 2 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "th.lwd\t" 4 { target { rv32 } } } } */ +/* { dg-final { scan-assembler-times "th.swd\t" 4 { target { rv32 } } } } */ |