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| author | Jan Beulich <jbeulich@suse.com> | 2023-07-19 10:11:11 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-07-19 10:11:11 +0200 |
| commit | fba96fd1b94bc9cd35302611be3ace0e21c97d6c (patch) | |
| tree | 0fce31d0ccd8f1746b98f269e2b1f1cda4781d57 | |
| parent | c5c7f1ef5ffcabb7dcbdc96571dbe1b0d675d4a5 (diff) | |
| download | gcc-fba96fd1b94bc9cd35302611be3ace0e21c97d6c.zip gcc-fba96fd1b94bc9cd35302611be3ace0e21c97d6c.tar.gz gcc-fba96fd1b94bc9cd35302611be3ace0e21c97d6c.tar.bz2 | |
x86: slightly enhance "vec_dupv2df<mask_name>"
Introduce a new alternative permitting all 32 registers to be used as
source without AVX512VL, by broadcasting to the full 512 bits in that
case. (The insn would also permit all registers to be used as
destination, but V2DFmode doesn't.)
gcc/
* config/i386/sse.md (vec_dupv2df<mask_name>): Add new AVX512F
alternative. Move AVX512VL part of condition to new "enabled"
attribute.
| -rw-r--r-- | gcc/config/i386/sse.md | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2d81347..35fd66e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -13784,18 +13784,27 @@ (set_attr "mode" "DF,DF,V1DF,V1DF,V1DF,V2DF,V1DF,V1DF,V1DF")]) (define_insn "vec_dupv2df<mask_name>" - [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,v") (vec_duplicate:V2DF - (match_operand:DF 1 "nonimmediate_operand" " 0,xm,vm")))] - "TARGET_SSE2 && <mask_avx512vl_condition>" + (match_operand:DF 1 "nonimmediate_operand" "0,xm,vm,vm")))] + "TARGET_SSE2" "@ unpcklpd\t%0, %0 %vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1} - vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}" - [(set_attr "isa" "noavx,sse3,avx512vl") - (set_attr "type" "sselog1") - (set_attr "prefix" "orig,maybe_vex,evex") - (set_attr "mode" "V2DF,DF,DF")]) + vmovddup\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1} + vbroadcastsd\t{%1, }%g0<mask_operand2>{|, %1}" + [(set_attr "isa" "noavx,sse3,avx512vl,*") + (set_attr "type" "sselog1,ssemov,ssemov,ssemov") + (set_attr "prefix" "orig,maybe_vex,evex,evex") + (set_attr "mode" "V2DF,DF,DF,V8DF") + (set (attr "enabled") + (cond [(eq_attr "alternative" "3") + (symbol_ref "TARGET_AVX512F && !TARGET_AVX512VL + && !TARGET_PREFER_AVX256") + (match_test "<mask_avx512vl_condition>") + (const_string "*") + ] + (symbol_ref "false")))]) (define_insn "vec_concatv2df" [(set (match_operand:V2DF 0 "register_operand" "=x,x,v,x,x, v,x,x") |