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authorXiaolong Chen <chenxiaolong@loongson.cn>2023-09-12 16:00:48 +0800
committerLulu Cheng <chenglulu@loongson.cn>2023-09-14 08:42:58 +0800
commitefba540049550ea72cb5d89cc4e213a5b9b2bf48 (patch)
tree3f74cb4fc998a55a86c8faf14018b1eb18b8c491
parent5ee9b286267ae19a8fb1b9efbb3d58b99d7cfcd1 (diff)
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LoongArch: Add tests for ASX xvldrepl/xvstelm instruction generation.
gcc/testsuite/ChangeLog: * gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c: New test. * gcc.target/loongarch/vector/lasx/lasx-xvstelm.c: New test.
-rw-r--r--gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c16
-rw-r--r--gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c14
2 files changed, 30 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c
new file mode 100644
index 0000000..1055679
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvldrepl.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mlasx" } */
+/* { dg-final { scan-assembler-times "xvldrepl.w" 2} } */
+
+#define N 258
+
+float a[N], b[N], c[N];
+
+void
+test ()
+{
+ for (int i = 0; i < 256; i++)
+ {
+ a[i] = c[0] * b[i] + c[1];
+ }
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c
new file mode 100644
index 0000000..1a7b0e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/lasx-xvstelm.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mlasx" } */
+/* { dg-final { scan-assembler-times "xvstelm.w" 8} } */
+
+#define LEN 256
+
+float a[LEN], b[LEN], c[LEN];
+
+void
+test ()
+{
+ for (int i = 0; i < LEN; i += 2)
+ a[i] = b[i] + c[i];
+}