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| author | Pan Li <pan2.li@intel.com> | 2024-07-18 11:30:38 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-07-18 17:01:17 +0800 |
| commit | ebac11afbcb7a52536da5f04fc524b870f5d76e0 (patch) | |
| tree | 047fd7b2682e46d2b6dc8d55a8247af57b9458d0 | |
| parent | 18f3b223b97011c2eab71c8e48c3a38a12ff8f65 (diff) | |
| download | gcc-ebac11afbcb7a52536da5f04fc524b870f5d76e0.zip gcc-ebac11afbcb7a52536da5f04fc524b870f5d76e0.tar.gz gcc-ebac11afbcb7a52536da5f04fc524b870f5d76e0.tar.bz2 | |
Doc: Add Standard-Names ustrunc and sstrunc for integer modes
This patch would like to add the doc for the Standard-Names
ustrunc and sstrunc, include both the scalar and vector integer
modes.
gcc/ChangeLog:
* doc/md.texi: Add Standard-Names ustrunc and sstrunc.
Signed-off-by: Pan Li <pan2.li@intel.com>
| -rw-r--r-- | gcc/doc/md.texi | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7f4335e..ecb7f34 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5543,6 +5543,18 @@ means of constraints requiring operands 1 and 0 to be the same location. @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} Similar, for other arithmetic operations. +@cindex @code{ustrunc@var{m}@var{n}2} instruction pattern +@item @samp{ustrunc@var{m}@var{n}2} +Truncate the operand 1, and storing the result in operand 0. There will +be saturation during the trunction. The result will be saturated to the +maximal value of operand 0 type if there is overflow when truncation. The +operand 1 must have mode @var{n}, and the operand 0 must have mode @var{m}. +Both scalar and vector integer modes are allowed. + +@cindex @code{sstrunc@var{m}@var{n}2} instruction pattern +@item @samp{sstrunc@var{m}@var{n}2} +Similar but for signed. + @cindex @code{andc@var{m}3} instruction pattern @item @samp{andc@var{m}3} Like @code{and@var{m}3}, but it uses bitwise-complement of operand 2 |