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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2024-05-07 22:59:44 +0200 |
|---|---|---|
| committer | Christoph Müllner <christoph.muellner@vrull.eu> | 2024-05-08 16:00:51 +0200 |
| commit | dd388198b8be52ab378c935fc517a269e0ba741c (patch) | |
| tree | 5095d447f39afcd1025810606084acdd4b28aad1 | |
| parent | b65cc09f9c78633a4f29d458a0549f36627c1259 (diff) | |
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RISC-V: Add test for sraiw-31 special case
We already optimize a sign-extension of a right-shift by 31 in
<optab>si3_extend. Let's add a test for that (similar to
zero-extend-1.c).
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sign-extend-1.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/sign-extend-1.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/sign-extend-1.c b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c new file mode 100644 index 0000000..e9056ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sign-extend-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target { riscv64*-*-* } } } */ +/* { dg-options "-march=rv64gc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ + +signed long +foo1 (int i) +{ + return i >> 31; +} +/* { dg-final { scan-assembler "sraiw\ta\[0-9\],a\[0-9\],31" } } */ + +/* { dg-final { scan-assembler-not "srai\t" } } */ +/* { dg-final { scan-assembler-not "srli\t" } } */ +/* { dg-final { scan-assembler-not "srliw\t" } } */ |