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| author | Haochen Jiang <haochen.jiang@intel.com> | 2024-04-24 10:43:18 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2024-04-24 15:21:27 +0800 |
| commit | d279c9d89b2f6ce89c1eec0ff4b980e9c5f51fd1 (patch) | |
| tree | 26fec9865d8a50df7cd5722f1f6554bafcfe3b54 | |
| parent | f952745943c2e9fbb2df32d2f2b037669d3fc50f (diff) | |
| download | gcc-d279c9d89b2f6ce89c1eec0ff4b980e9c5f51fd1.zip gcc-d279c9d89b2f6ce89c1eec0ff4b980e9c5f51fd1.tar.gz gcc-d279c9d89b2f6ce89c1eec0ff4b980e9c5f51fd1.tar.bz2 | |
i386: Fix behavior for both using AVX10.1-256 in options and function attribute
When we are using -mavx10.1-256 in command line and avx10.1-256 in
target attribute together, zmm should never be generated. But current
GCC will generate zmm since it wrongly enables EVEX512 for non-explicitly
set AVX512. This patch will fix that issue.
gcc/ChangeLog:
* config/i386/i386-options.cc (ix86_valid_target_attribute_tree):
Check whether AVX512F is explicitly enabled.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_1-24.c: New test.
| -rw-r--r-- | gcc/config/i386/i386-options.cc | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/avx10_1-24.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 68a2e1c..ac48b5c 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -1431,6 +1431,7 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, scenario. */ if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256) && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F) + && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F) && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512) && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512; diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c b/gcc/testsuite/gcc.target/i386/avx10_1-24.c new file mode 100644 index 0000000..2e93f04 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-24.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ +/* { dg-final { scan-assembler-not "%zmm" } } */ + +typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__)); + +void __attribute__((target("avx10.1-256"))) callee256(__m512 *a, __m512 *b) { *a = *b; } |