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| author | Patrick O'Neill <patrick@rivosinc.com> | 2023-04-07 10:44:09 -0700 |
|---|---|---|
| committer | Patrick O'Neill <patrick@rivosinc.com> | 2023-05-02 13:08:04 -0700 |
| commit | bff7c77386447936dd614ebc7086b826c99c6642 (patch) | |
| tree | 0d4ed8463e02c38fb2cbdd93477671e5723c68f2 | |
| parent | 942ab49b5f8955371cf5db23608ba5f5f5244152 (diff) | |
| download | gcc-bff7c77386447936dd614ebc7086b826c99c6642.zip gcc-bff7c77386447936dd614ebc7086b826c99c6642.tar.gz gcc-bff7c77386447936dd614ebc7086b826c99c6642.tar.bz2 | |
RISC-V: Weaken mem_thread_fence
This change brings atomic fences in line with table A.6 of the ISA
manual.
Relax mem_thread_fence according to the memmodel given.
2023-04-27 Patrick O'Neill <patrick@rivosinc.com>
gcc/ChangeLog:
* config/riscv/sync.md (mem_thread_fence_1): Change fence
depending on the given memory model.
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
| -rw-r--r-- | gcc/config/riscv/sync.md | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 3e6345e..ba132d8 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -45,14 +45,24 @@ DONE; }) -;; Until the RISC-V memory model (hence its mapping from C++) is finalized, -;; conservatively emit a full FENCE. (define_insn "mem_thread_fence_1" [(set (match_operand:BLK 0 "" "") (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\tiorw,iorw") + { + enum memmodel model = (enum memmodel) INTVAL (operands[1]); + model = memmodel_base (model); + if (model == MEMMODEL_SEQ_CST) + return "fence\trw,rw"; + else if (model == MEMMODEL_ACQ_REL) + return "fence.tso"; + else if (model == MEMMODEL_ACQUIRE) + return "fence\tr,rw"; + else if (model == MEMMODEL_RELEASE) + return "fence\trw,w"; + } + [(set (attr "length") (const_int 4))]) ;; Atomic memory operations. |