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| author | Pan Li <pan2.li@intel.com> | 2023-07-20 16:31:10 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-07-20 16:38:55 +0800 |
| commit | bb42f05d0738bddc721e838ebe9993df39ff2e0f (patch) | |
| tree | 553d1e0da7b18d9486588af2ded612031ca2ff42 | |
| parent | 097106972f243ddcbddbbddd9a6bcc076f58b453 (diff) | |
| download | gcc-bb42f05d0738bddc721e838ebe9993df39ff2e0f.zip gcc-bb42f05d0738bddc721e838ebe9993df39ff2e0f.tar.gz gcc-bb42f05d0738bddc721e838ebe9993df39ff2e0f.tar.bz2 | |
RISC-V: Fix one incorrect match operand for RVV reduction
There are 2 of the RVV reduction pattern mask operand takes
vector_merge_operand instead of vector_mask_operand by mistake. This
patch would like to fix this.
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect match_operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr110299-1.c: Adjust tests.
* gcc.target/riscv/rvv/base/pr110299-2.c: Ditto.
| -rw-r--r-- | gcc/config/riscv/vector.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index fcff3ee3..f745888 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7915,7 +7915,7 @@ (unspec:VSF_LMUL1 [(unspec:VSF_LMUL1 [(unspec:<VHF:VM> - [(match_operand:<VHF:VM> 1 "vector_merge_operand" "vmWc1,vmWc1") + [(match_operand:<VHF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") @@ -7937,7 +7937,7 @@ (unspec:VDF_LMUL1 [(unspec:VDF_LMUL1 [(unspec:<VSF:VM> - [(match_operand:<VSF:VM> 1 "vector_merge_operand" "vmWc1,vmWc1") + [(match_operand:<VSF:VM> 1 "vector_mask_operand" "vmWc1,vmWc1") (match_operand 5 "vector_length_operand" " rK, rK") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c index d83eea9..a903dde 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c @@ -3,5 +3,5 @@ #include "pr110299-1.h" -/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c index cdcde1b..1254ace 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c @@ -4,5 +4,5 @@ #include "pr110299-1.h" #include "pr110299-2.h" -/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */ -/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 3 } } */ +/* { dg-final { scan-assembler-times {vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */ |