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| author | Alan Lawrence <alan.lawrence@arm.com> | 2014-12-18 15:00:51 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2014-12-18 15:00:51 +0000 |
| commit | b5b34d375969883ecb2de5d4912603faebc83299 (patch) | |
| tree | 34445fb90808b144f6e80c2b4f3485d6cda25d51 | |
| parent | 26e0ff941167ba78f0052a94b79a0a347753d3e6 (diff) | |
| download | gcc-b5b34d375969883ecb2de5d4912603faebc83299.zip gcc-b5b34d375969883ecb2de5d4912603faebc83299.tar.gz gcc-b5b34d375969883ecb2de5d4912603faebc83299.tar.bz2 | |
[AArch64] Simplify patterns for sshr_n_[us]64 intrinsic
* config/aarch64/aarch64.md (enum "unspec"): Remove UNSPEC_SSHR64.
* config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): Change shift
amount to 63 if was 64.
(aarch64_sshr_simddi): Remove.
From-SVN: r218867
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 19 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 1 |
3 files changed, 13 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6d5bb44..3bb1dae 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2014-12-18 Alan Lawrence <alan.lawrence@arm.com> + + * config/aarch64/aarch64.md (enum "unspec"): Remove UNSPEC_SSHR64. + + * config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): Change shift + amount to 63 if was 64. + (aarch64_sshr_simddi): Remove. + 2014-12-18 Wilco Dijkstra <wilco.dijkstra@arm.com> * gcc/config/aarch64/aarch64.c (TARGET_MIN_DIVISIONS_FOR_RECIP_MUL): diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index d4256a5..9a48537 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -726,25 +726,16 @@ (match_operand:SI 2 "aarch64_shift_imm64_di" "")] "TARGET_SIMD" { + /* An arithmetic shift right by 64 fills the result with copies of the sign + bit, just like asr by 63 - however the standard pattern does not handle + a shift by 64. */ if (INTVAL (operands[2]) == 64) - emit_insn (gen_aarch64_sshr_simddi (operands[0], operands[1])); - else - emit_insn (gen_ashrdi3 (operands[0], operands[1], operands[2])); + operands[2] = GEN_INT (63); + emit_insn (gen_ashrdi3 (operands[0], operands[1], operands[2])); DONE; } ) -;; SIMD shift by 64. This pattern is a special case as standard pattern does -;; not handle NEON shifts by 64. -(define_insn "aarch64_sshr_simddi" - [(set (match_operand:DI 0 "register_operand" "=w") - (unspec:DI - [(match_operand:DI 1 "register_operand" "w")] UNSPEC_SSHR64))] - "TARGET_SIMD" - "sshr\t%d0, %d1, 64" - [(set_attr "type" "neon_shift_imm")] -) - (define_expand "vlshr<mode>3" [(match_operand:VDQ_BHSI 0 "register_operand" "") (match_operand:VDQ_BHSI 1 "register_operand" "") diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index a0ee362..ebde276 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -107,7 +107,6 @@ UNSPEC_SISD_SSHL UNSPEC_SISD_USHL UNSPEC_SSHL_2S - UNSPEC_SSHR64 UNSPEC_ST1 UNSPEC_ST2 UNSPEC_ST3 |