diff options
| author | Alan Lawrence <alan.lawrence@arm.com> | 2014-12-18 15:20:11 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2014-12-18 15:20:11 +0000 |
| commit | 8448880117087e77aaf6bcfc4398f4b0442db1b1 (patch) | |
| tree | 6748c14b1a0f6ce0386167928ed111a611610ecc | |
| parent | b5b34d375969883ecb2de5d4912603faebc83299 (diff) | |
| download | gcc-8448880117087e77aaf6bcfc4398f4b0442db1b1.zip gcc-8448880117087e77aaf6bcfc4398f4b0442db1b1.tar.gz gcc-8448880117087e77aaf6bcfc4398f4b0442db1b1.tar.bz2 | |
[AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsic
gcc/:
* config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): Handle shift
by 64 by moving const0_rtx.
(aarch64_ushr_simddi): Delete.
* config/aarch64/aarch64.md (enum unspec): Delete UNSPEC_USHR64.
gcc/testsuite/:
* gcc.target/aarch64/ushr64_1.c: Remove scan-assembler "ushr...64".
From-SVN: r218868
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 13 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 1 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/ushr64_1.c | 1 |
5 files changed, 13 insertions, 14 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3bb1dae..1fd5b4f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,13 @@ 2014-12-18 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64-simd.md (aarch64_lshr_simddi): Handle shift + by 64 by moving const0_rtx. + (aarch64_ushr_simddi): Delete. + + * config/aarch64/aarch64.md (enum unspec): Delete UNSPEC_USHR64. + +2014-12-18 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64.md (enum "unspec"): Remove UNSPEC_SSHR64. * config/aarch64/aarch64-simd.md (aarch64_ashr_simddi): Change shift diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 9a48537..52a1c3b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -756,24 +756,13 @@ "TARGET_SIMD" { if (INTVAL (operands[2]) == 64) - emit_insn (gen_aarch64_ushr_simddi (operands[0], operands[1])); + emit_move_insn (operands[0], const0_rtx); else emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2])); DONE; } ) -;; SIMD shift by 64. This pattern is a special case as standard pattern does -;; not handle NEON shifts by 64. -(define_insn "aarch64_ushr_simddi" - [(set (match_operand:DI 0 "register_operand" "=w") - (unspec:DI - [(match_operand:DI 1 "register_operand" "w")] UNSPEC_USHR64))] - "TARGET_SIMD" - "ushr\t%d0, %d1, 64" - [(set_attr "type" "neon_shift_imm")] -) - (define_expand "vec_set<mode>" [(match_operand:VDQ_BHSI 0 "register_operand") (match_operand:<VEL> 1 "register_operand") diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index ebde276..12532c1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -117,7 +117,6 @@ UNSPEC_TLS UNSPEC_TLSDESC UNSPEC_USHL_2S - UNSPEC_USHR64 UNSPEC_VSTRUCTDUMMY UNSPEC_SP_SET UNSPEC_SP_TEST diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 025dfce..f7e72ed 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2014-12-18 Alan Lawrence <alan.lawrence@arm.com> + + * gcc.target/aarch64/ushr64_1.c: Remove scan-assembler "ushr...64". + 2014-12-18 Martin Liska <mliska@suse.cz> * g++.dg/ipa/pr64146.C: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/ushr64_1.c b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c index b1c741d..ee49489 100644 --- a/gcc/testsuite/gcc.target/aarch64/ushr64_1.c +++ b/gcc/testsuite/gcc.target/aarch64/ushr64_1.c @@ -42,7 +42,6 @@ test_vshrd_n_u64_0 (uint64_t passed, uint64_t expected) return vshrd_n_u64 (passed, 0) != expected; } -/* { dg-final { scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 64" 2 } } */ /* { dg-final { (scan-assembler-times "ushr\\td\[0-9\]+, d\[0-9\]+, 4" 2) || \ (scan-assembler-times "lsr\\tx\[0-9\]+, x\[0-9\]+, 4" 2) } } */ /* { dg-final { scan-assembler-not "ushr\\td\[0-9\]+, d\[0-9\]+, 0" } } */ |