RISC-V: Add testcases for unsigned imm vec SAT_SUB form1

form1:
void __attribute__((noinline))             \
vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit)  \
{                                                   \
  unsigned i;                                       \
  for (i = 0; i < limit; i++)                       \
    out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0;  \
}

Passed the rv64gcv full regression test.

Signed-off-by: Li Xu <xuli1@eswincomputing.com>

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h: add data for vec sat_sub.
	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: add unsigned imm vec sat_sub form1.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c: New test.

10 files changed, 406 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h
index 32edc35..bcb4a3f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_data.h
@@ -253,6 +253,246 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_add_imm)[][2][N] =
   },
 };
 
+uint8_t TEST_UNARY_DATA(uint8_t, sat_u_sub_imm)[][2][N] =
+{
+  { /* For sub imm 0 */
+    {
+      0, 1, 5, 255,
+      0, 1, 5, 255,
+      0, 1, 5, 255,
+      0, 1, 5, 255,
+    },
+    {
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 1 */
+    {
+      0, 1, 2, 8,
+      0, 1, 2, 8,
+      0, 1, 2, 8,
+      0, 1, 2, 8,
+    },
+    {
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 254 */
+    {
+      0, 1, 254, 255,
+      0, 1, 254, 255,
+      0, 1, 254, 255,
+      0, 1, 254, 255,
+    },
+    {
+      254, 253, 0, 0,
+      254, 253, 0, 0,
+      254, 253, 0, 0,
+      254, 253, 0, 0,
+    },
+  },
+  { /* For sub imm 255 */
+    {
+      0, 1, 5, 255,
+      0, 1, 5, 255,
+      0, 1, 5, 255,
+      0, 1, 5, 255,
+    },
+    {
+      255, 254, 250, 0,
+      255, 254, 250, 0,
+      255, 254, 250, 0,
+      255, 254, 250, 0,
+    },
+  },
+};
+
+uint16_t TEST_UNARY_DATA(uint16_t, sat_u_sub_imm)[][2][N] =
+{
+  { /* For sub imm 0 */
+    {
+      0, 1, 5, 65535,
+      0, 1, 5, 65535,
+      0, 1, 5, 65535,
+      0, 1, 5, 65535,
+    },
+    {
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 1 */
+    {
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+    },
+    {
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 65534 */
+    {
+      0, 1, 65534, 65535,
+      0, 1, 65534, 65535,
+      0, 1, 65534, 65535,
+      0, 1, 65534, 65535,
+    },
+    {
+      65534, 65533, 0, 0,
+      65534, 65533, 0, 0,
+      65534, 65533, 0, 0,
+      65534, 65533, 0, 0,
+    },
+  },
+  { /* For sub imm 65535 */
+    {
+      0, 1, 65534, 65535,
+      0, 1, 65534, 65535,
+      0, 1, 65534, 65535,
+      0, 1, 65534, 65535,
+    },
+    {
+      65535, 65534, 1, 0,
+      65535, 65534, 1, 0,
+      65535, 65534, 1, 0,
+      65535, 65534, 1, 0,
+    },
+  },
+};
+
+uint32_t TEST_UNARY_DATA(uint32_t, sat_u_sub_imm)[][2][N] =
+{
+  { /* For sub imm 0 */
+    {
+      0, 1, 5, 4294967295,
+      0, 1, 5, 4294967295,
+      0, 1, 5, 4294967295,
+      0, 1, 5, 4294967295,
+    },
+    {
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 1 */
+    {
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+    },
+    {
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 4294967294 */
+    {
+      0, 1, 4294967294, 4294967295,
+      0, 1, 4294967294, 4294967295,
+      0, 1, 4294967294, 4294967295,
+      0, 1, 4294967294, 4294967295,
+    },
+    {
+      4294967294, 4294967293, 0, 0,
+      4294967294, 4294967293, 0, 0,
+      4294967294, 4294967293, 0, 0,
+      4294967294, 4294967293, 0, 0,
+    },
+  },
+  { /* For sub imm 4294967295 */
+    {
+      0, 1, 4294967294, 4294967295,
+      0, 1, 4294967294, 4294967295,
+      0, 1, 4294967294, 4294967295,
+      0, 1, 4294967294, 4294967295,
+    },
+    {
+      4294967295, 4294967294, 1, 0,
+      4294967295, 4294967294, 1, 0,
+      4294967295, 4294967294, 1, 0,
+      4294967295, 4294967294, 1, 0,
+    },
+  },
+};
+
+uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] =
+{
+  { /* For sub imm 0 */
+    {
+      0, 1, 5, 18446744073709551615u,
+      0, 1, 5, 18446744073709551615u,
+      0, 1, 5, 18446744073709551615u,
+      0, 1, 5, 18446744073709551615u,
+    },
+    {
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+      0, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 1 */
+    {
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+      0, 1, 5, 8,
+    },
+    {
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+      1, 0, 0, 0,
+    },
+  },
+  { /* For sub imm 18446744073709551614 */
+    {
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+    },
+    {
+      18446744073709551614u, 18446744073709551613u, 0, 0,
+      18446744073709551614u, 18446744073709551613u, 0, 0,
+      18446744073709551614u, 18446744073709551613u, 0, 0,
+      18446744073709551614u, 18446744073709551613u, 0, 0,
+    },
+  },
+  { /* For sub imm 18446744073709551615 */
+    {
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+      0, 1, 18446744073709551614u, 18446744073709551615u,
+    },
+    {
+      18446744073709551615u, 18446744073709551614u, 1, 0,
+      18446744073709551615u, 18446744073709551614u, 1, 0,
+      18446744073709551615u, 18446744073709551614u, 1, 0,
+      18446744073709551615u, 18446744073709551614u, 1, 0,
+    },
+  },
+};
+
 #define TEST_BINARY_DATA_NAME(T1, T2, NAME) test_bin_##T1##_##T2##_##NAME##_data
 #define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \
   TEST_BINARY_DATA_NAME(T1, T2, NAME)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c
new file mode 100644
index 0000000..52192d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-1.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint8_t, 10)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c
new file mode 100644
index 0000000..b161ff0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint16_t, 70)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c
new file mode 100644
index 0000000..13c8cf5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-3.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint32_t, 5)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c
new file mode 100644
index 0000000..5ed237b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1(uint64_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c
new file mode 100644
index 0000000..19d3bb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-1.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint8_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 254)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 255)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+  RUN (T, out, d[0][0], d[0][1],   0, N);
+  RUN (T, out, d[1][0], d[1][1],   1, N);
+  RUN (T, out, d[2][0], d[2][1], 254, N);
+  RUN (T, out, d[3][0], d[3][1], 255, N);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c
new file mode 100644
index 0000000..f304d82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-2.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint16_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65534)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 65535)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+  RUN (T, out, d[0][0], d[0][1],   0, N);
+  RUN (T, out, d[1][0], d[1][1],   1, N);
+  RUN (T, out, d[2][0], d[2][1], 65534, N);
+  RUN (T, out, d[3][0], d[3][1], 65535, N);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c
new file mode 100644
index 0000000..283d37f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-3.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint32_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967294)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 4294967295)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+  RUN (T, out, d[0][0], d[0][1],   0, N);
+  RUN (T, out, d[1][0], d[1][1],   1, N);
+  RUN (T, out, d[2][0], d[2][1], 4294967294, N);
+  RUN (T, out, d[3][0], d[3][1], 4294967295, N);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c
new file mode 100644
index 0000000..2512975
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_imm-run-4.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint64_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   0)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T,   1)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551614u)
+DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP (T, 18446744073709551615u)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_sub_imm);
+
+  RUN (T, out, d[0][0], d[0][1],   0, N);
+  RUN (T, out, d[1][0], d[1][1],   1, N);
+  RUN (T, out, d[2][0], d[2][1], 18446744073709551614u, N);
+  RUN (T, out, d[3][0], d[3][1], 18446744073709551615u, N);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index c2e52a4..cb419553 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -468,6 +468,24 @@ vec_sat_u_sub_##T1##_##T2##_fmt_zip (T1 *x, T2 b, unsigned limit) \
 }
 #define DEF_VEC_SAT_U_SUB_ZIP_WRAP(T1, T2) DEF_VEC_SAT_U_SUB_ZIP(T1, T2)
 
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM) \
+void __attribute__((noinline))             \
+vec_sat_u_sub_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit)  \
+{                                                   \
+  unsigned i;                                       \
+  for (i = 0; i < limit; i++)                       \
+    out[i] = (T)IMM >= in[i] ? (T)IMM - in[i] : 0;  \
+}
+
+#define DEF_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, IMM) \
+  DEF_VEC_SAT_U_SUB_IMM_FMT_1(T, IMM)
+
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N) \
+  vec_sat_u_sub_imm##IMM##_##T##_fmt_1(out, op_1, N);             \
+  VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_U_SUB_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \
+  RUN_VEC_SAT_U_SUB_IMM_FMT_1(T, out, op_1, expect, IMM, N)
+
 #define DEF_VEC_SAT_S_SUB_FMT_1(T, UT, MIN, MAX)                     \
 void __attribute__((noinline))                                       \
 vec_sat_s_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \