diff options
| author | Richard Biener <rguenther@suse.de> | 2024-09-05 11:38:04 +0200 |
|---|---|---|
| committer | Richard Biener <rguenth@gcc.gnu.org> | 2024-09-05 13:58:27 +0200 |
| commit | 7b8da316089bfdf299592a88fdab2f93c444b03a (patch) | |
| tree | 9003f5ffc9cf8d240ae1d296288ccc9095ee186a | |
| parent | 2379cbb94b2668227c237c94c82e3c49fe39fd0f (diff) | |
| download | gcc-7b8da316089bfdf299592a88fdab2f93c444b03a.zip gcc-7b8da316089bfdf299592a88fdab2f93c444b03a.tar.gz gcc-7b8da316089bfdf299592a88fdab2f93c444b03a.tar.bz2 | |
[AARCH64] adjust gcc.target/aarch64/sve/mask_gather_load_7.c
The following adjusts the scan-assembler to also allow predicate
registers p8-15 to be used for the destination of the compares.
I see that code generation with a pending vectorizer patch (the
only assembler change is different predicate register allocation).
* gcc.target/aarch64/sve/mask_gather_load_7.c: Allow
p8-15 to be used for the destination of the compares.
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_7.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_7.c b/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_7.c index c31fae3..7812ae7 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_7.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/mask_gather_load_7.c @@ -41,13 +41,13 @@ TEST_ALL (TEST_LOOP) /* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.h, p[0-7]/z, \[x[0-9]+, x[0-9]+, lsl 1\]\n} 36 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 12 } } */ -/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-7]\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-9]+\.h, p[0-7]/z, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+\.s, sxtw 2\]\n} 18 } } */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, z[0-9]+\.s, uxtw 2\]\n} 18 } } */ /* Also used for the TEST32 indices. */ /* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.s, p[0-7]/z, \[x[0-9]+, x[0-9]+, lsl 2\]\n} 72 } } */ -/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 12 } } */ -/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-7]\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tcmpeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 12 } } */ +/* { dg-final { scan-assembler-times {\tfcmeq\tp[0-9]+\.s, p[0-7]/z, z[0-9]+\.s, z[0-9]+\.s\n} 6 } } */ /* { dg-final { scan-assembler-times {\tld1d\tz[0-9]+\.d, p[0-7]/z, \[x[0-9]+, z[0-9]+\.d, lsl 3\]\n} 36 } } */ |