arm: Add cde feature support for Cortex-M55 CPU.

This patch adds cde feature (optional) support for Cortex-M55 CPU, please refer
[1] for more details. To use this feature we need to specify +cdecpN
(e.g. -mcpu=cortex-m55+cdecp<N>), where N is the coprocessor number 0 to 7.

gcc/ChangeLog:

2023-01-13  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* common/config/arm/arm-common.cc (arm_canon_arch_option_1): Ignore cde
	options for -mlibarch.
	* config/arm/arm-cpus.in (begin cpu cortex-m55): Add cde options.
	* doc/invoke.texi (CDE): Document options for Cortex-M55 CPU.

gcc/testsuite/ChangeLog:

2023-01-13  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

	* gcc.target/arm/multilib.exp: Add multilib tests for Cortex-M55 CPU.

4 files changed, 36 insertions, 9 deletions

diff --git a/gcc/common/config/arm/arm-common.cc b/gcc/common/config/arm/arm-common.cc
index c38812f..9ed6830 100644
--- a/gcc/common/config/arm/arm-common.cc
+++ b/gcc/common/config/arm/arm-common.cc
@@ -685,8 +685,10 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib)
   auto_sbitmap target_isa (isa_num_bits);
   auto_sbitmap base_isa (isa_num_bits);
   auto_sbitmap fpu_isa (isa_num_bits);
+  auto_sbitmap ignore_multilib_isa (isa_num_bits);
 
   bitmap_clear (fpu_isa);
+  bitmap_clear (ignore_multilib_isa);
 
   const arch_option *selected_arch = NULL;
 
@@ -719,15 +721,6 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib)
       arm_initialize_isa (target_isa, selected_arch->common.isa_bits);
       arm_parse_option_features (target_isa, &selected_arch->common,
 				 strchr (arch, '+'));
-      if (arch_for_multilib)
-	{
-	  const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
-						     isa_nobit};
-	  sbitmap isa_bits = sbitmap_alloc (isa_num_bits);
-	  arm_initialize_isa (isa_bits, removable_bits);
-	  bitmap_and_compl (target_isa, target_isa, isa_bits);
-	}
-
       if (fpu && strcmp (fpu, "auto") != 0)
 	{
 	  /* We assume that architectures do not have any FPU bits
@@ -806,6 +799,16 @@ arm_canon_arch_option_1 (int argc, const char **argv, bool arch_for_multilib)
       bitmap_clear_bit (target_isa, isa_bit_vfpv2);
     }
 
+  /* Here we remove feature isa bits from -mlibarch string which are not
+     necessary for multilib string comparsion.  */
+  if ((arch || cpu) && arch_for_multilib)
+    {
+      const enum isa_feature removable_bits[] = {ISA_IGNORE_FOR_MULTILIB,
+						 isa_nobit};
+      arm_initialize_isa (ignore_multilib_isa, removable_bits);
+      bitmap_and_compl (target_isa, target_isa, ignore_multilib_isa);
+    }
+
   /* If we don't have a selected architecture by now, something's
      badly wrong.  */
   gcc_assert (selected_arch);
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index e89106c..579cf35 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1644,6 +1644,14 @@ begin cpu cortex-m55
  option nomve remove mve mve_float
  option nofp remove ALL_FP mve_float
  option nodsp remove MVE mve_float
+ option cdecp0 add cdecp0
+ option cdecp1 add cdecp1
+ option cdecp2 add cdecp2
+ option cdecp3 add cdecp3
+ option cdecp4 add cdecp4
+ option cdecp5 add cdecp5
+ option cdecp6 add cdecp6
+ option cdecp7 add cdecp7
  isa quirk_no_asmcpu quirk_vlldm
  costs v7m
  vendor 41
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 701c228..0b0bdb6 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -22168,6 +22168,10 @@ floating-point instructions on @samp{cortex-m55}.
 Disable the M-Profile Vector Extension (MVE) single precision floating-point
 instructions on @samp{cortex-m55}.
 
+@item +cdecp0, +cdecp1, ... , +cdecp7
+Enable the Custom Datapath Extension (CDE) on selected coprocessors according
+to the numbers given in the options in the range 0 to 7 on @samp{cortex-m55}.
+
 @item  +nofp
 Disables the floating-point instructions on @samp{arm9e},
 @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp
index f903f02..e9c9b9c 100644
--- a/gcc/testsuite/gcc.target/arm/multilib.exp
+++ b/gcc/testsuite/gcc.target/arm/multilib.exp
@@ -854,6 +854,18 @@ if {[multilib_config "rmprofile"] } {
 	{-mcpu=cortex-m55+nomve+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp"
 	{-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-mcpu=cortex-m55+nodsp+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m55 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m55+cdecp0 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=hard -mfpu=auto} "thumb/v8-m.main+dp/hard"
+	{-mcpu=cortex-m55 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m55+cdecp0 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=softfp -mfpu=auto} "thumb/v8-m.main+dp/softfp"
+	{-mcpu=cortex-m55 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m55+cdecp0 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m55+nomve+cdecp0 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp"
+	{-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7 -mfloat-abi=soft -mfpu=auto} "thumb/v8-m.main/nofp"
 	{-march=armv8-m.main+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-march=armv8-m.main+fp+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"
 	{-march=armv8-m.main+fp.dp+cdecp0 -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp"