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| author | Jonathan Wright <jonathan.wright@arm.com> | 2021-05-14 14:49:47 +0100 |
|---|---|---|
| committer | Jonathan Wright <jonathan.wright@arm.com> | 2021-05-19 14:44:26 +0100 |
| commit | 778ac63fe244b63380bd3b2dee4d20ff27332bce (patch) | |
| tree | b23d7e73f336ef0f85504fc3a9f4662d5fef1add | |
| parent | 4e26303e0b90038473e3d7490dc0369a74866b1b (diff) | |
| download | gcc-778ac63fe244b63380bd3b2dee4d20ff27332bce.zip gcc-778ac63fe244b63380bd3b2dee4d20ff27332bce.tar.gz gcc-778ac63fe244b63380bd3b2dee4d20ff27332bce.tar.bz2 | |
aarch64: Relax aarch64_sqxtun2<mode> RTL pattern
Use UNSPEC_SQXTUN instead of UNSPEC_SQXTUN2 in aarch64_sqxtun2<mode>
patterns. This allows for more more aggressive combinations and
ultimately better code generation. The now redundant UNSPEC_SQXTUN2
is removed.
gcc/ChangeLog:
2021-05-14 Jonathn Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd.md: Use UNSPEC_SQXTUN instead
of UNSPEC_SQXTUN2.
* config/aarch64/iterators.md: Remove UNSPEC_SQXTUN2.
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 1 |
2 files changed, 3 insertions, 4 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 5473d61..7952309 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4859,7 +4859,7 @@ (vec_concat:<VNARROWQ2> (match_operand:<VNARROWQ> 1 "register_operand" "0") (unspec:<VNARROWQ> - [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2)))] + [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN)))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" "sqxtun2\\t%0.<V2ntype>, %2.<Vtype>" [(set_attr "type" "neon_sat_shift_imm_narrow_q")] @@ -4869,7 +4869,7 @@ [(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w") (vec_concat:<VNARROWQ2> (unspec:<VNARROWQ> - [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN2) + [(match_operand:VQN 2 "register_operand" "w")] UNSPEC_SQXTUN) (match_operand:<VNARROWQ> 1 "register_operand" "0")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" "sqxtun2\\t%0.<V2ntype>, %2.<Vtype>" @@ -4880,7 +4880,7 @@ [(match_operand:<VNARROWQ2> 0 "register_operand") (match_operand:<VNARROWQ> 1 "register_operand") (unspec:<VNARROWQ> - [(match_operand:VQN 2 "register_operand")] UNSPEC_SQXTUN2)] + [(match_operand:VQN 2 "register_operand")] UNSPEC_SQXTUN)] "TARGET_SIMD" { if (BYTES_BIG_ENDIAN) diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 29ce669..0ec93b0 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -521,7 +521,6 @@ UNSPEC_USQADD ; Used in aarch64-simd.md. UNSPEC_SUQADD ; Used in aarch64-simd.md. UNSPEC_SQXTUN ; Used in aarch64-simd.md. - UNSPEC_SQXTUN2 ; Used in aarch64-simd.md. UNSPEC_SSRA ; Used in aarch64-simd.md. UNSPEC_USRA ; Used in aarch64-simd.md. UNSPEC_SRSRA ; Used in aarch64-simd.md. |