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| author | Oleg Endo <olegendo@gcc.gnu.org> | 2024-07-21 14:11:21 +0900 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2024-07-21 14:30:58 +0900 |
| commit | 58b78cf068b3b24c11d7812a5f4de865e9cdb8b4 (patch) | |
| tree | ee2dd0262a92b01fcdaf95065f012797504ed2b6 | |
| parent | 6d811c15e622572749a2e84d3884cb5ce3296578 (diff) | |
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SH: Fix outage caused by recently added 2nd combine pass after reg alloc
I've also confirmed on the CSiBE set that the secondary combine pass is
actually beneficial on SH. It does result in some code size reductions.
gcc/CHangeLog:
* config/sh/sh.md (mov_neg_si_t): Allow insn and split after
register allocation.
(*treg_noop_move): New insn.
| -rw-r--r-- | gcc/config/sh/sh.md | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 3e97825..7eee12c 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -8408,7 +8408,7 @@ gcc_assert (t_reg_operand (operands[1], VOIDmode)); return "subc %0,%0"; } - "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)" + "&& !t_reg_operand (operands[1], VOIDmode)" [(const_int 0)] { sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn); @@ -8421,6 +8421,14 @@ } [(set_attr "type" "arith")]) +;; no-op T bit move which can result from other optimizations. +(define_insn_and_split "*treg_noop_move" + [(set (reg:SI T_REG) (reg:SI T_REG))] + "TARGET_SH1" + "#" + "&& 1" + [(const_int 0)]) + ;; Invert the T bit. ;; On SH2A we can use the nott insn. On anything else this must be done with ;; multiple insns like: |