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| author | Raphael Moreira Zinsly <rzinsly@ventanamicro.com> | 2024-07-22 11:23:17 -0300 |
|---|---|---|
| committer | Raphael Moreira Zinsly <rzinsly@ventanamicro.com> | 2024-08-09 10:48:53 -0300 |
| commit | 5694fcf75b65bea5d3eb42e5d28d7f3e5ee7cfd7 (patch) | |
| tree | d72f97191a87c00b1ae6f77fc3e785d9b8730795 | |
| parent | 0e604d0ef6dcac8ee4cdc62902f2a2708ef7b040 (diff) | |
| download | gcc-5694fcf75b65bea5d3eb42e5d28d7f3e5ee7cfd7.zip gcc-5694fcf75b65bea5d3eb42e5d28d7f3e5ee7cfd7.tar.gz gcc-5694fcf75b65bea5d3eb42e5d28d7f3e5ee7cfd7.tar.bz2 | |
RISC-V: Move riscv_v_adjust_scalable_frame
Move riscv_v_adjust_scalable_frame () in preparation for the stack clash
protection support.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_v_adjust_scalable_frame): Move
closer to riscv_expand_prologue.
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 6981ec4..eb32520 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3122,37 +3122,6 @@ riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src) } } -/* Adjust scalable frame of vector for prologue && epilogue. */ - -static void -riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue) -{ - rtx tmp = RISCV_PROLOGUE_TEMP (Pmode); - rtx adjust_size = RISCV_PROLOGUE_TEMP2 (Pmode); - rtx insn, dwarf, adjust_frame_rtx; - - riscv_legitimize_poly_move (Pmode, adjust_size, tmp, - gen_int_mode (offset, Pmode)); - - if (epilogue) - insn = gen_add3_insn (target, target, adjust_size); - else - insn = gen_sub3_insn (target, target, adjust_size); - - insn = emit_insn (insn); - - RTX_FRAME_RELATED_P (insn) = 1; - - adjust_frame_rtx - = gen_rtx_SET (target, - plus_constant (Pmode, target, epilogue ? offset : -offset)); - - dwarf = alloc_reg_note (REG_FRAME_RELATED_EXPR, copy_rtx (adjust_frame_rtx), - NULL_RTX); - - REG_NOTES (insn) = dwarf; -} - /* Take care below subreg const_poly_int move: 1. (set (subreg:DI (reg:TI 237) 8) @@ -7931,6 +7900,37 @@ static const code_for_push_pop_t code_for_push_pop[ZCMP_MAX_GRP_SLOTS][ZCMP_OP_N code_for_gpr_multi_popret_up_to_s11, code_for_gpr_multi_popretz_up_to_s11}}; +/* Adjust scalable frame of vector for prologue && epilogue. */ + +static void +riscv_v_adjust_scalable_frame (rtx target, poly_int64 offset, bool epilogue) +{ + rtx tmp = RISCV_PROLOGUE_TEMP (Pmode); + rtx adjust_size = RISCV_PROLOGUE_TEMP2 (Pmode); + rtx insn, dwarf, adjust_frame_rtx; + + riscv_legitimize_poly_move (Pmode, adjust_size, tmp, + gen_int_mode (offset, Pmode)); + + if (epilogue) + insn = gen_add3_insn (target, target, adjust_size); + else + insn = gen_sub3_insn (target, target, adjust_size); + + insn = emit_insn (insn); + + RTX_FRAME_RELATED_P (insn) = 1; + + adjust_frame_rtx + = gen_rtx_SET (target, + plus_constant (Pmode, target, epilogue ? offset : -offset)); + + dwarf = alloc_reg_note (REG_FRAME_RELATED_EXPR, copy_rtx (adjust_frame_rtx), + NULL_RTX); + + REG_NOTES (insn) = dwarf; +} + static rtx riscv_gen_multi_push_pop_insn (riscv_zcmp_op_t op, HOST_WIDE_INT adj_size, unsigned int regs_num) |