RISC-V: Refine the testcase of vector SAT_SUB

Take scan-assembler-times for vssub insn check instead of function body,
as we only care about if we can generate the fixed point insn vssub.

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Remove
	func body check and take scan asm times instead.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

44 files changed, 92 insertions, 496 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
index bd8fbc1..b989cb6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
index 52c2a68..b2fc988 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
index 37fde86..944b197 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
index c6f33cf..862fd41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
index 4262209..edadbf0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
index 9d16b83..d3eadae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
index f673839..b9f61fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
index cd9af17..8171a3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_4(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
index f74f075..4e1f655 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
index 0f8f909..d259675 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
index 9b627e6..19aaa7e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
index d2d0c04..5ed44d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
index cab2938..ea95a37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_5(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
index 7826108..9fee795 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
index 04a2c58..de8defc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
index eb7dac6..aed21c7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
index 6a15511..8bfe35d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_6(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
index 4611ac7..7554929 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
index ee0853d..7994bbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
index 7af569d9..2f2665d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
index 70ae929..0c181e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_7(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
index 1ff020f..b1fd6f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
index 3dde5f2..e67da17 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
index b658c22..ca18727 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
index df1435d..203776e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
index 77e3323..6aed879 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_8(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
index 4885dda..b5caadb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
index 33d69e1..eaa7b33 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
index a050e0d..f885b2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
index 0abb6e0..4f5ab41 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_9:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_9(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
index f40f56d..aa90e04 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
index 7031f16..becaa6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
index 0cc1298..e104793 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
index 00a6719..0efdf65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_1(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
index 2aba688..c73b98e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_10:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_10(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
index 86cd920..6c42573 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
index d8880e5..cde2465 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
index 6ba1d1b..5399519 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint32_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
index b3e40ed..ade479e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint64_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_2(uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
index ffc68e7..6221f18a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
@@ -1,18 +1,9 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint8_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_FMT_3(uint8_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
index 1386f52..674206b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
@@ -1,22 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_trunc_uint8_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
-** ...
-** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
-** ...
-** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
index 959e2e1..32e828c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
@@ -1,22 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_trunc_uint16_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
-** ...
-** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
-** ...
-** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
index 769e0af..72afd08 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
@@ -1,22 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_trunc_uint32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
-** ...
-** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
-** ...
-** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vncvt\.x\.x\.w} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c
index 29b32f3..16ff0c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_zip.c
@@ -1,18 +1,10 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
 
 #include "../vec_sat_arith.h"
 
-/*
-** vec_sat_u_sub_uint16_t_uint32_t_fmt_zip:
-** ...
-** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** ...
-** vrgather\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
 DEF_VEC_SAT_U_SUB_ZIP_WRAP(uint16_t, uint32_t)
 
 /* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */
+/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */