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| author | Claudio Bantaloukas <claudio.bantaloukas@arm.com> | 2024-11-11 18:08:28 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2024-11-11 18:08:28 +0000 |
| commit | 2ad277478620037103379ffad6a99dc00bf0bca7 (patch) | |
| tree | dc3ebfaf3dc38ebd455490c0a619b7eb0a683344 | |
| parent | 416a8b375589d4c2891b437d0991296ef32bde98 (diff) | |
| download | gcc-2ad277478620037103379ffad6a99dc00bf0bca7.zip gcc-2ad277478620037103379ffad6a99dc00bf0bca7.tar.gz gcc-2ad277478620037103379ffad6a99dc00bf0bca7.tar.bz2 | |
aarch64: return scalar fp8 values in fp registers
According to the aapcs64: If the argument is an 8-bit (...) precision
Floating-point or short vector type and the NSRN is less than 8, then the
argument is allocated to the least significant bits of register v[NSRN].
gcc/
* config/aarch64/aarch64.cc
(aarch64_vfp_is_call_or_return_candidate): use fp registers to
return svmfloat8_t parameters.
gcc/testsuite/
* gcc.target/aarch64/fp8_scalar_1.c:
| -rw-r--r-- | gcc/config/aarch64/aarch64.cc | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c | 4 |
2 files changed, 4 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index e9cee0a..00bcf18 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -22306,7 +22306,8 @@ aarch64_vfp_is_call_or_return_candidate (machine_mode mode, if ((!composite_p && (GET_MODE_CLASS (mode) == MODE_FLOAT - || GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT)) + || GET_MODE_CLASS (mode) == MODE_DECIMAL_FLOAT + || (type && TYPE_MAIN_VARIANT (type) == aarch64_mfp8_type_node))) || aarch64_short_vector_p (type, mode)) { *count = 1; diff --git a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c index 1bc2ac2..61edf06 100644 --- a/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c +++ b/gcc/testsuite/gcc.target/aarch64/fp8_scalar_1.c @@ -7,10 +7,10 @@ /* **stacktest1: +** umov w0, v0.b\[0\] ** sub sp, sp, #16 -** and w0, w0, 255 ** strb w0, \[sp, 15\] -** ldrb w0, \[sp, 15\] +** ldr b0, \[sp, 15\] ** add sp, sp, 16 ** ret */ |