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| author | Pan Li <pan2.li@intel.com> | 2024-09-13 09:16:48 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-09-19 07:38:32 +0800 |
| commit | 1d1687513400c1b805bf5924f732c21dbf166ae8 (patch) | |
| tree | 237a0f2f75481aa8e10794f039acd88de09ea460 | |
| parent | aa338bdd46a4946e9d5ac0923ce9bf9bc621c852 (diff) | |
| download | gcc-1d1687513400c1b805bf5924f732c21dbf166ae8.zip gcc-1d1687513400c1b805bf5924f732c21dbf166ae8.tar.gz gcc-1d1687513400c1b805bf5924f732c21dbf166ae8.tar.bz2 | |
RISC-V: Fix signed SAT_ADD test case for int64_t
The int8_t test for signed SAT_ADD is sat_s_add-1.c, the sat_s_add-4.c
should be for int64_t. Thus, update sat_s_add-4.c for int64_t type.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sat_s_add-4.c: Update test for int64_t
instead of int8_t.
Signed-off-by: Pan Li <pan2.li@intel.com>
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/sat_s_add-4.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c b/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c index f85675c..12c9540 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-4.c @@ -5,26 +5,25 @@ #include "sat_arith.h" /* -** sat_s_add_int8_t_fmt_1: +** sat_s_add_int64_t_fmt_1: ** add\s+[atx][0-9]+,\s*a0,\s*a1 ** xor\s+[atx][0-9]+,\s*a0,\s*a1 ** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 ** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 ** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 +** li\s+[atx][0-9]+,\s*-1 +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 +** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** neg\s+[atx][0-9]+,\s*[atx][0-9]+ ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 ** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ ** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 ** ret */ -DEF_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ |