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| author | Yangyu Chen <chenyangyu@isrc.iscas.ac.cn> | 2024-10-14 18:31:06 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-10-14 19:53:17 +0800 |
| commit | 1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1 (patch) | |
| tree | b11f42cfd996dc7bb18188894fb9cb05b2da4e21 | |
| parent | accb85345edb91368221fd07b74e74df427b7de0 (diff) | |
| download | gcc-1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1.zip gcc-1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1.tar.gz gcc-1c507a02f29c6ca735f40f4b16b341ce9d5aa1b1.tar.bz2 | |
RISC-V: Add detailed comments on processing implied extensions. [NFC]
In some cases, we don't need to handle implied extensions. Add detailed
comments to help developers understand what implied ISAs should be
considered.
libgcc/ChangeLog:
* config/riscv/feature_bits.c (__init_riscv_features_bits_linux):
Add detailed comments on processing implied extensions.
Signed-off-by: Yangyu Chen <chenyangyu@isrc.iscas.ac.cn>
| -rw-r--r-- | libgcc/config/riscv/feature_bits.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/libgcc/config/riscv/feature_bits.c b/libgcc/config/riscv/feature_bits.c index 9bdbc46..a90e553 100644 --- a/libgcc/config/riscv/feature_bits.c +++ b/libgcc/config/riscv/feature_bits.c @@ -290,9 +290,12 @@ static void __init_riscv_features_bits_linux () } const struct riscv_hwprobe hwprobe_ima_ext = hwprobes[4]; - /* Every time we add new extensions, we should check if previous extensions - imply the new extension and set the corresponding bit. */ + imply the new extension and set the corresponding bit. + We don't need to handle cases where: + 1. The new extension implies a previous extension (e.g., Zve32f -> F). + 2. The extensions imply some other extensions appear in the same release + version of Linux Kernel (e.g., Zbc - > Zbkc). */ if (hwprobe_ima_ext.value & RISCV_HWPROBE_IMA_FD) { @@ -397,7 +400,7 @@ __init_riscv_feature_bits () #ifdef __linux __init_riscv_features_bits_linux (); #else - /* Unsupported, just initlizaed that into all zeros. */ + /* Unsupported, just initialize that into all zeros. */ __riscv_feature_bits.length = 0; __riscv_vendor_feature_bits.length = 0; __riscv_cpu_model.mvendorid = 0; |