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| author | YunQiang Su <yunqiang.su@cipunited.com> | 2022-01-26 03:21:20 +0000 |
|---|---|---|
| committer | YunQiang Su <yunqiang.su@cipunited.com> | 2022-04-01 06:57:27 +0000 |
| commit | 15d683d4f0b390b27c54a7c92c6e4f33195bdc93 (patch) | |
| tree | 9ac8b550bd66fc6651da055da80da9f6a0a0ffe2 | |
| parent | 5901a10bdf7a872697894f2e0990bff8b2e48c39 (diff) | |
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MIPS: IPL is 8bit in Cause and Status registers if TARGET_MCU
If MIPS MCU extension is enable, the IPL section in Cause and Status
registers has been expand to 8bit instead of 6bit.
In Cause: the bits are 10-17.
In Status: the bits are 10-16 and 18.
MD00834-2B-MUCON-AFP-01.03.pdf: P49 and P61.
gcc/ChangeLog:
* config/mips/mips.cc (mips_expand_prologue):
IPL is 8bit for MCU ASE.
| -rw-r--r-- | gcc/config/mips/mips.cc | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index a1c4b43..91e1e96 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -12254,10 +12254,22 @@ mips_expand_prologue (void) /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ if (!cfun->machine->keep_interrupts_masked_p && cfun->machine->int_mask == INT_MASK_EIC) - emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), - GEN_INT (6), + { + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), + TARGET_MCU ? GEN_INT (7) : GEN_INT (6), GEN_INT (SR_IPL), gen_rtx_REG (SImode, K0_REG_NUM))); + if (TARGET_MCU) + { + emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), + gen_rtx_REG (SImode, K0_REG_NUM), + GEN_INT (7))); + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), + GEN_INT (1), + GEN_INT (SR_IPL+8), + gen_rtx_REG (SImode, K0_REG_NUM))); + } + } /* Clear all interrupt mask bits up to and including the handler's interrupt line. */ |