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| author | Julian Brown <julian@codesourcery.com> | 2021-06-17 10:52:51 -0700 |
|---|---|---|
| committer | Julian Brown <julian@codesourcery.com> | 2021-06-29 08:19:56 -0700 |
| commit | 0c06e46a81d86d70d788ca1a93d27b6902bd4dc1 (patch) | |
| tree | 3a68b9668ab6107f690498ed1176fa3d31d65a50 | |
| parent | 8f332122589f97b9c974b168ca5b0b186296f0e4 (diff) | |
| download | gcc-0c06e46a81d86d70d788ca1a93d27b6902bd4dc1.zip gcc-0c06e46a81d86d70d788ca1a93d27b6902bd4dc1.tar.gz gcc-0c06e46a81d86d70d788ca1a93d27b6902bd4dc1.tar.bz2 | |
amdgcn: Add clrsbsi2/clrsbdi2 implementation
This patch adds an open-coded implementation of the clrsb<mode>2
(count leading redundant sign bit) standard names using the GCN flbit_i*
instructions for SImode and DImode. Those don't count exactly as we need,
so we need a couple of other instructions to fix up the result afterwards.
These patterns are lost from libgcc if we build it for DImode/TImode
rather than SImode/DImode, a change we make in a later patch in this
series.
2021-06-18 Julian Brown <julian@codesourcery.com>
gcc/
* config/gcn/gcn.md (UNSPEC_FLBIT_INT): New unspec constant.
(s_mnemonic): Add clrsb.
(gcn_flbit<mode>_int): Add insn pattern for SImode/DImode.
(clrsb<mode>2): Add expander for SImode/DImode.
| -rw-r--r-- | gcc/config/gcn/gcn.md | 40 |
1 files changed, 38 insertions, 2 deletions
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index 82f7a46..ae7249a 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -81,7 +81,8 @@ UNSPEC_MOV_FROM_LANE63 UNSPEC_GATHER UNSPEC_SCATTER - UNSPEC_RCP]) + UNSPEC_RCP + UNSPEC_FLBIT_INT]) ;; }}} ;; {{{ Attributes @@ -338,7 +339,8 @@ [(not "not%b") (popcount "bcnt1_i32%b") (clz "flbit_i32%b") - (ctz "ff1_i32%b")]) + (ctz "ff1_i32%b") + (clrsb "flbit_i32%i")]) (define_code_attr revmnemonic [(minus "subrev%i") @@ -1611,6 +1613,40 @@ [(set_attr "type" "sop1") (set_attr "length" "4,8")]) +(define_insn "gcn_flbit<mode>_int" + [(set (match_operand:SI 0 "register_operand" "=Sg,Sg") + (unspec:SI [(match_operand:SIDI 1 "gcn_alu_operand" "SgA, B")] + UNSPEC_FLBIT_INT))] + "" + { + if (<MODE>mode == SImode) + return "s_flbit_i32\t%0, %1"; + else + return "s_flbit_i32_i64\t%0, %1"; + } + [(set_attr "type" "sop1") + (set_attr "length" "4,8")]) + +(define_expand "clrsb<mode>2" + [(set (match_operand:SI 0 "register_operand" "") + (clrsb:SI (match_operand:SIDI 1 "gcn_alu_operand" "")))] + "" + { + rtx tmp = gen_reg_rtx (SImode); + /* FLBIT_I* counts sign or zero bits at the most-significant end of the + input register (and returns -1 for 0/-1 inputs). We want the number of + *redundant* bits (i.e. that value minus one), and an answer of 31/63 for + 0/-1 inputs. We can do that in three instructions... */ + emit_insn (gen_gcn_flbit<mode>_int (tmp, operands[1])); + emit_insn (gen_uminsi3 (tmp, tmp, + gen_int_mode (GET_MODE_BITSIZE (<MODE>mode), + SImode))); + /* If we put this last, it can potentially be folded into a subsequent + arithmetic operation. */ + emit_insn (gen_subsi3 (operands[0], tmp, const1_rtx)); + DONE; + }) + ;; }}} ;; {{{ ALU: generic 32-bit binop |