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author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:09:19 +0000 |
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committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:09:19 -0700 |
commit | fff6304f52e3dc48b2e26683e1260fda977cbd86 (patch) | |
tree | f001ead8a79152388a4b01400a52cf7743b682a5 | |
parent | 5d48867be5b9fa92d3c171418eb5d46f2ad6d640 (diff) | |
download | gcc-fff6304f52e3dc48b2e26683e1260fda977cbd86.zip gcc-fff6304f52e3dc48b2e26683e1260fda977cbd86.tar.gz gcc-fff6304f52e3dc48b2e26683e1260fda977cbd86.tar.bz2 |
i386: Emulate MMX <any_logic><mode>3 with SSE
Emulate MMX <any_logic><mode>3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:mmx_<code><mode>3): Also allow
TARGET_MMX_WITH_SSE.
(any_logic:<code><mode>3): New.
(any_logic:*mmx_<code><mode>3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
From-SVN: r271222
-rw-r--r-- | gcc/ChangeLog | 9 | ||||
-rw-r--r-- | gcc/config/i386/mmx.md | 33 |
2 files changed, 32 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ecf9f7b..7bee150 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,15 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (any_logic:mmx_<code><mode>3): Also allow + TARGET_MMX_WITH_SSE. + (any_logic:<code><mode>3): New. + (any_logic:*mmx_<code><mode>3): Also allow TARGET_MMX_WITH_SSE. + Add SSE support. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_ashr<mode>3): Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. (mmx_<shift_insn><mode>3): Likewise. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 73110b5..058d805 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1086,20 +1086,33 @@ (define_expand "mmx_<code><mode>3" [(set (match_operand:MMXMODEI 0 "register_operand") (any_logic:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand") - (match_operand:MMXMODEI 2 "nonimmediate_operand")))] - "TARGET_MMX" + (match_operand:MMXMODEI 1 "register_mmxmem_operand") + (match_operand:MMXMODEI 2 "register_mmxmem_operand")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") + +(define_expand "<code><mode>3" + [(set (match_operand:MMXMODEI 0 "register_operand") + (any_logic:MMXMODEI + (match_operand:MMXMODEI 1 "register_operand") + (match_operand:MMXMODEI 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);") (define_insn "*mmx_<code><mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (any_logic:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" - "p<logic>\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + (match_operand:MMXMODEI 1 "register_mmxmem_operand" "%0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)" + "@ + p<logic>\t{%2, %0|%0, %2} + p<logic>\t{%2, %0|%0, %2} + vp<logic>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; |