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| author | Sudakshina Das <sudi.das@arm.com> | 2017-06-02 15:32:41 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2017-06-02 15:32:41 +0000 |
| commit | ffa8a92137cd41829d477be4ef1c1c28849ffee1 (patch) | |
| tree | 87ea0cd2ba57089fdd06b051c2c1ca7ba7142895 | |
| parent | b160939bf3cd072e1c7a05bbbe221040f7670df2 (diff) | |
| download | gcc-ffa8a92137cd41829d477be4ef1c1c28849ffee1.zip gcc-ffa8a92137cd41829d477be4ef1c1c28849ffee1.tar.gz gcc-ffa8a92137cd41829d477be4ef1c1c28849ffee1.tar.bz2 | |
[PATCH][AArch64] Allow CMP+SHIFT when comparing with zero
gcc/
* config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for
comparision with zero.
gcc/testsuite/
* gcc.target/aarch64/cmp_shifted_reg_1.c: New.
From-SVN: r248836
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c | 11 |
4 files changed, 21 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 079f1fd..070bb8f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-06-02 Sudakshina Das <sudi.das@arm.com> + + * config/aarch64/aarch64.c (aarch64_select_cc_mode): Return CC_SWP for + comparision with zero. + 2017-06-02 Will Schmidt <will_schmidt@vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vec_min and vec_max builtins. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 7064f05..5707e53 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4767,7 +4767,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) the comparison will have to be swapped when we emit the assembly code. */ if ((GET_MODE (x) == SImode || GET_MODE (x) == DImode) - && (REG_P (y) || GET_CODE (y) == SUBREG) + && (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx) && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 70a8335..2f38470 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-06-02 Sudakshina Das <sudi.das@arm.com> + + * gcc.target/aarch64/cmp_shifted_reg_1.c: New. + 2017-06-02 Will Schmidt <will_schmidt@vnet.ibm.com> * gcc.target/powerpc/fold-vec-minmax-char.c: New. diff --git a/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c new file mode 100644 index 0000000..cacecf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/cmp_shifted_reg_1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 " } */ + +int f3 (int x, int y) +{ + int res = x << 3; + return res != 0; +} + +/* We should combine the shift and compare */ +/* { dg-final { scan-assembler "cmp\.*\twzr, w\[0-9\]+, lsl 3" } } */ |