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| author | Jan Beulich <jbeulich@suse.com> | 2019-07-22 08:07:29 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@gcc.gnu.org> | 2019-07-22 08:07:29 +0000 |
| commit | ff8f129bc2f57fdfc80f56d73b84a80948d11d84 (patch) | |
| tree | d2b45aae47701a32eb7af6c7c4b813c5a2644a73 | |
| parent | a861990d21a7f495695597e75509a834d44fdb2d (diff) | |
| download | gcc-ff8f129bc2f57fdfc80f56d73b84a80948d11d84.zip gcc-ff8f129bc2f57fdfc80f56d73b84a80948d11d84.tar.gz gcc-ff8f129bc2f57fdfc80f56d73b84a80948d11d84.tar.bz2 | |
x86/AVX512: improve generated code for bit-wise negation of vectors of integers
NOT on vectors of integers does not require loading a constant vector of
all ones into a register - VPTERNLOG can be used here (and could/should
be further used to carry out other binary and ternary logical operations
which don't have a special purpose instruction).
gcc/
2019-07-22 Jan Beulich <jbeulich@suse.com>
* config/i386/sse.md (ternlogsuffix): New.
(one_cmpl<mode>2): Don't force CONSTM1_RTX into a register when
AVX512F is in use.
(<mask_codefor>one_cmpl<mode>2<mask_name>): New.
From-SVN: r273663
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 22 |
2 files changed, 28 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 05d8efa..3e861ef 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-07-22 Jan Beulich <jbeulich@suse.com> + + * config/i386/sse.md (ternlogsuffix): New. + (one_cmpl<mode>2): Don't force CONSTM1_RTX into a register when + AVX512F is in use. + (<mask_codefor>one_cmpl<mode>2<mask_name>): New. + 2019-07-22 Martin Liska <mliska@suse.cz> * config/avr/avr.c (avr_asm_output_aligned_decl_common): Update diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 12d6dc0..8abd161 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -853,6 +853,13 @@ (V4SF "k") (V2DF "q") (SF "k") (DF "q")]) +;; Mapping of vector modes to VPTERNLOG suffix +(define_mode_attr ternlogsuffix + [(V8DI "q") (V4DI "q") (V2DI "q") + (V16SI "d") (V8SI "d") (V4SI "d") + (V32HI "d") (V16HI "d") (V8HI "d") + (V64QI "d") (V32QI "d") (V16QI "d")]) + ;; Number of scalar elements in each vector type (define_mode_attr ssescalarnum [(V64QI "64") (V16SI "16") (V8DI "8") @@ -12723,9 +12730,22 @@ (match_dup 2)))] "TARGET_SSE" { - operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode)); + if (!TARGET_AVX512F) + operands[2] = force_reg (<MODE>mode, CONSTM1_RTX (<MODE>mode)); + else + operands[2] = CONSTM1_RTX (<MODE>mode); }) +(define_insn "<mask_codefor>one_cmpl<mode>2<mask_name>" + [(set (match_operand:VI 0 "register_operand" "=v") + (xor:VI (match_operand:VI 1 "nonimmediate_operand" "vm") + (match_operand:VI 2 "vector_all_ones_operand" "BC")))] + "TARGET_AVX512F" + "vpternlog<ternlogsuffix>\t{$0x55, %1, %0, %0<mask_operand3>|%0<mask_operand3>, %0, %1, 0x55}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + (define_expand "<sse2_avx2>_andnot<mode>3" [(set (match_operand:VI_AVX2 0 "register_operand") (and:VI_AVX2 |