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| author | Alan Lawrence <alan.lawrence@arm.com> | 2014-12-19 17:48:15 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2014-12-19 17:48:15 +0000 |
| commit | fe82d1f27edc59a5c5cdb705235bd341cab2dbb9 (patch) | |
| tree | 8d7747ebe7777be2fb70a60a341a6863a4ff06a5 | |
| parent | f1f1391ce029d83261560db18bd9c1f442221c5e (diff) | |
| download | gcc-fe82d1f27edc59a5c5cdb705235bd341cab2dbb9.zip gcc-fe82d1f27edc59a5c5cdb705235bd341cab2dbb9.tar.gz gcc-fe82d1f27edc59a5c5cdb705235bd341cab2dbb9.tar.bz2 | |
[AArch64 2/3] Add SIMD-reg variants of logical operators and/ior/xor/not
* config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2):
Add SIMD-register variant.
* config/aarch64/iterators.md (Vbtype): Add value for SI.
From-SVN: r218960
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 25 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 3 |
3 files changed, 24 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f27d698..10b5538 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2014-12-19 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64.md (<optab><mode>3, one_cmpl<mode>2): + Add SIMD-register variant. + * config/aarch64/iterators.md (Vbtype): Add value for SI. + +2014-12-19 Alan Lawrence <alan.lawrence@arm.com> + * config/aarch64/aarch64.md (subdi3, adddi3_aarch64): Don't penalize SIMD reg variant. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 3e84346..bc9138d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2866,12 +2866,16 @@ ;; ------------------------------------------------------------------- (define_insn "<optab><mode>3" - [(set (match_operand:GPI 0 "register_operand" "=r,rk") - (LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r") - (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")))] + [(set (match_operand:GPI 0 "register_operand" "=r,rk,w") + (LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r,w") + (match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>,w")))] "" - "<logical>\\t%<w>0, %<w>1, %<w>2" - [(set_attr "type" "logic_reg,logic_imm")] + "@ + <logical>\\t%<w>0, %<w>1, %<w>2 + <logical>\\t%<w>0, %<w>1, %<w>2 + <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>" + [(set_attr "type" "logic_reg,logic_imm,neon_logic") + (set_attr "simd" "*,*,yes")] ) ;; zero_extend version of above @@ -2992,11 +2996,14 @@ ) (define_insn "one_cmpl<mode>2" - [(set (match_operand:GPI 0 "register_operand" "=r") - (not:GPI (match_operand:GPI 1 "register_operand" "r")))] + [(set (match_operand:GPI 0 "register_operand" "=r,w") + (not:GPI (match_operand:GPI 1 "register_operand" "r,w")))] "" - "mvn\\t%<w>0, %<w>1" - [(set_attr "type" "logic_reg")] + "@ + mvn\\t%<w>0, %<w>1 + mvn\\t%0.8b, %1.8b" + [(set_attr "type" "logic_reg,neon_logic") + (set_attr "simd" "*,yes")] ) (define_insn "*one_cmpl_<optab><mode>2" diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 16a2647..26e3ebc 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -387,7 +387,8 @@ (V2SI "8b") (V4SI "16b") (V2DI "16b") (V2SF "8b") (V4SF "16b") (V2DF "16b") - (DI "8b") (DF "8b")]) + (DI "8b") (DF "8b") + (SI "8b")]) ;; Define element mode for each vector mode. (define_mode_attr VEL [(V8QI "QI") (V16QI "QI") |