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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2017-01-27 15:59:02 +0000 |
|---|---|---|
| committer | William Schmidt <wschmidt@gcc.gnu.org> | 2017-01-27 15:59:02 +0000 |
| commit | f75bbf3fc68e1e03b55ae1f60c861faf213968ab (patch) | |
| tree | 21e42eae3834af6b4fc09535ff6414a6b85dd4a8 | |
| parent | 46f7b80ec41b680de9316dbdb3c9cfe376d8e88b (diff) | |
| download | gcc-f75bbf3fc68e1e03b55ae1f60c861faf213968ab.zip gcc-f75bbf3fc68e1e03b55ae1f60c861faf213968ab.tar.gz gcc-f75bbf3fc68e1e03b55ae1f60c861faf213968ab.tar.bz2 | |
re PR testsuite/65484 (FAIL: g++.dg/vect/pr36648.cc on powerpc64)
2017-01-27 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
PR target/65484
* g++.dg/vect/pr36648.cc: Modify to reflect that the loop is not
vectorized on POWER unless hardware misaligned loads are
available.
From-SVN: r244985
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/g++.dg/vect/pr36648.cc | 9 |
2 files changed, 14 insertions, 2 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2dce32e..f326e40 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2017-01-27 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/65484 + * g++.dg/vect/pr36648.cc: Modify to reflect that the loop is not + vectorized on POWER unless hardware misaligned loads are + available. + 2017-01-27 Bin Cheng <bin.cheng@arm.com> PR rtl-optimization/78559 diff --git a/gcc/testsuite/g++.dg/vect/pr36648.cc b/gcc/testsuite/g++.dg/vect/pr36648.cc index 198de0e..7bda828 100644 --- a/gcc/testsuite/g++.dg/vect/pr36648.cc +++ b/gcc/testsuite/g++.dg/vect/pr36648.cc @@ -19,7 +19,12 @@ Foo foo; int main() { } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! vect_no_align } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect_no_align } } } } */ +/* On older powerpc hardware (POWER7 and earlier), the default flag + -mno-allow-movmisalign prevents vectorization. On POWER8 and later, + when vect_hw_misalign is true, vectorization occurs. For other + targets, ! vect_no_align is a sufficient test. */ + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { { { ! vect_no_align } && { ! powerpc*-*-* } } || { powerpc*-*-* && vect_hw_misalign } } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { { { ! vect_no_align } && { ! powerpc*-*-* } } || { powerpc*-*-* && vect_hw_misalign } } } } } */ |