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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-11-14 12:07:03 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-11-14 12:07:03 +0000 |
| commit | f6b9a2a0c58a6f8b29f801fd1631c7eee5138c3a (patch) | |
| tree | 98019cdbfc5bf0bc0b95561471186e3aee3edc48 | |
| parent | 94f7a25eebd2599175e838f09afe7daf59c3e9c1 (diff) | |
| download | gcc-f6b9a2a0c58a6f8b29f801fd1631c7eee5138c3a.zip gcc-f6b9a2a0c58a6f8b29f801fd1631c7eee5138c3a.tar.gz gcc-f6b9a2a0c58a6f8b29f801fd1631c7eee5138c3a.tar.bz2 | |
The second patch updates the Cortex-A57 scheduler now that we can differentiate between shifts and bitfield inserts.
The second patch updates the Cortex-A57 scheduler now that we can differentiate
between shifts and bitfield inserts. The Cortex-A57 Software Optimization Guide
indicates that BFM operations use the integer multi-cycle pipeline, while ARM
UXTB/H instructions use the Integer 1 or Integer 0 pipelines, so swap the bfm
and extend reservations. This results in minor scheduling differences.
* config/arm/cortex-a57.md (cortex_a57_alu): Move extend here, bfm...
(cortex_a57_alu_shift): ...here.
From-SVN: r242385
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/arm/cortex-a57.md | 4 |
2 files changed, 7 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 07173ab..e1306dc 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2016-11-14 Wilco Dijkstra <wdijkstr@arm.com> + * config/arm/cortex-a57.md (cortex_a57_alu): Move extend here, bfm... + (cortex_a57_alu_shift): ...here. + +2016-11-14 Wilco Dijkstra <wdijkstr@arm.com> + * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3) Use bfx attribute. (aarch64_lshr_sisd_or_int_<mode>3): Likewise. diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md index da46184..6307250 100644 --- a/gcc/config/arm/cortex-a57.md +++ b/gcc/config/arm/cortex-a57.md @@ -297,7 +297,7 @@ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\ + adr,bfx,extend,clz,rbit,rev,alu_dsp_reg,\ rotate_imm,shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ @@ -307,7 +307,7 @@ ;; ALU ops with immediate shift (define_insn_reservation "cortex_a57_alu_shift" 3 (and (eq_attr "tune" "cortexa57") - (eq_attr "type" "extend,\ + (eq_attr "type" "bfm,\ alu_shift_imm,alus_shift_imm,\ crc,logic_shift_imm,logics_shift_imm,\ mov_shift,mvn_shift")) |