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| author | Alan Lawrence <alan.lawrence@arm.com> | 2015-09-15 12:28:20 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2015-09-15 12:28:20 +0000 |
| commit | f4720b94c49fa64aad75c309681712f0e94a5059 (patch) | |
| tree | 358e96d7d76f4eb0ebe6b906c3507cc6973ef055 | |
| parent | 6960bf558f2e6076c901cd57f2c24b5462d8d311 (diff) | |
| download | gcc-f4720b94c49fa64aad75c309681712f0e94a5059.zip gcc-f4720b94c49fa64aad75c309681712f0e94a5059.tar.gz gcc-f4720b94c49fa64aad75c309681712f0e94a5059.tar.bz2 | |
[AArch64 array_mode 3/8] Stop using EImode in aarch64-simd.md and iterators.md
* config/aarch64/aarch64-simd.md (aarch64_simd_ld3r<mode>):
Change operand mode from <V_THREE_ELEM> to BLK.
(aarch64_vec_load_lanesci_lane<mode>): Likewise.
(aarch64_vec_store_lanesci_lane<mode>): Likewise.
(aarch64_ld3r<mode>): Generate MEM rtx with BLKmode, call set_mem_size.
(aarch64_ld3_lane<mode>): Likewise.
(aarch64_st3_lane<mode>): Likewise.
* config/aarch64/iterators.md (V_THREE_ELEM): Remove.
From-SVN: r227783
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 26 | ||||
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 9 |
3 files changed, 24 insertions, 22 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index affc5ba..44373e1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2015-09-08 Alan Lawrence <alan.lawrence@arm.com> + + * config/aarch64/aarch64-simd.md (aarch64_simd_ld3r<mode>): + Change operand mode from <V_THREE_ELEM> to BLK. + (aarch64_vec_load_lanesci_lane<mode>): Likewise. + (aarch64_vec_store_lanesci_lane<mode>): Likewise. + (aarch64_ld3r<mode>): Generate MEM rtx with BLKmode, call set_mem_size. + (aarch64_ld3_lane<mode>): Likewise. + (aarch64_st3_lane<mode>): Likewise. + * config/aarch64/iterators.md (V_THREE_ELEM): Remove. + 2015-09-15 Alan Lawrence <alan.lawrence@arm.com> * config/aarch64/aarch64-simd.md diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 20b9be9..c1048d3 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4026,7 +4026,7 @@ (define_insn "aarch64_simd_ld3r<mode>" [(set (match_operand:CI 0 "register_operand" "=w") - (unspec:CI [(match_operand:<V_THREE_ELEM> 1 "aarch64_simd_struct_operand" "Utv") + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ] UNSPEC_LD3_DUP))] "TARGET_SIMD" @@ -4036,7 +4036,7 @@ (define_insn "aarch64_vec_load_lanesci_lane<mode>" [(set (match_operand:CI 0 "register_operand" "=w") - (unspec:CI [(match_operand:<V_THREE_ELEM> 1 "aarch64_simd_struct_operand" "Utv") + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") (match_operand:CI 2 "register_operand" "0") (match_operand:SI 3 "immediate_operand" "i") (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] @@ -4080,11 +4080,11 @@ ;; RTL uses GCC vector extension indices, so flip only for assembly. (define_insn "aarch64_vec_store_lanesci_lane<mode>" - [(set (match_operand:<V_THREE_ELEM> 0 "aarch64_simd_struct_operand" "=Utv") - (unspec:<V_THREE_ELEM> [(match_operand:CI 1 "register_operand" "w") - (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) - (match_operand:SI 2 "immediate_operand" "i")] - UNSPEC_ST3_LANE))] + [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv") + (unspec:BLK [(match_operand:CI 1 "register_operand" "w") + (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) + (match_operand:SI 2 "immediate_operand" "i")] + UNSPEC_ST3_LANE))] "TARGET_SIMD" { operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); @@ -4400,8 +4400,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = <V_THREE_ELEM>mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3); emit_insn (gen_aarch64_simd_ld3r<mode> (operands[0], mem)); DONE; @@ -4625,8 +4625,8 @@ (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] "TARGET_SIMD" { - machine_mode mode = <V_THREE_ELEM>mode; - rtx mem = gen_rtx_MEM (mode, operands[1]); + rtx mem = gen_rtx_MEM (BLKmode, operands[1]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3); emit_insn (gen_aarch64_vec_load_lanesci_lane<mode> (operands[0], mem, @@ -4905,8 +4905,8 @@ (match_operand:SI 2 "immediate_operand")] "TARGET_SIMD" { - machine_mode mode = <V_THREE_ELEM>mode; - rtx mem = gen_rtx_MEM (mode, operands[0]); + rtx mem = gen_rtx_MEM (BLKmode, operands[0]); + set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 3); emit_insn (gen_aarch64_vec_store_lanesci_lane<mode> (mem, operands[1], diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index e311b88..ca0d299 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -604,15 +604,6 @@ (V4HF "SF") (V8HF "SF") (DF "V2DI") (V2DF "V2DI")]) -;; Similar, for three elements. -(define_mode_attr V_THREE_ELEM [(V8QI "BLK") (V16QI "BLK") - (V4HI "BLK") (V8HI "BLK") - (V2SI "BLK") (V4SI "BLK") - (DI "EI") (V2DI "EI") - (V2SF "BLK") (V4SF "BLK") - (V4HF "BLK") (V8HF "BLK") - (DF "EI") (V2DF "EI")]) - ;; Similar, for four elements. (define_mode_attr V_FOUR_ELEM [(V8QI "SI") (V16QI "SI") (V4HI "V4HI") (V8HI "V4HI") |