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authorUros Bizjak <uros@gcc.gnu.org>2013-12-26 01:05:44 +0100
committerUros Bizjak <uros@gcc.gnu.org>2013-12-26 01:05:44 +0100
commitf313cce5c0dae5c0ef31cd01b4a7421032b88d68 (patch)
treed87323d17db4626057a1870d478c1207d9d72cb0
parentb97de419c269933d065a5b30ea2c828966eb30c8 (diff)
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driver-i386.c (decode_caches_intel): Add missing entries.
* config/i386/driver-i386.c (decode_caches_intel): Add missing entries. From-SVN: r206203
-rw-r--r--gcc/ChangeLog16
-rw-r--r--gcc/config/i386/driver-i386.c18
2 files changed, 27 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b7740743..0b851a5 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,16 +1,18 @@
+2013-12-26 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/driver-i386.c (decode_caches_intel): Add missing entries.
+
2013-12-25 H.J. Lu <hongjiu.lu@intel.com>
PR target/59587
- * config/i386/i386.c (struct ptt): Add a field for processor
- name.
- (processor_target_table): Sync with processor_type. Add
- processor names.
+ * config/i386/i386.c (struct ptt): Add a field for processor name.
+ (processor_target_table): Sync with processor_type.
+ Add processor names.
(cpu_names): Removed.
(ix86_option_override_internal): Default x_ix86_tune_string
to processor_target_table[TARGET_CPU_DEFAULT].name.
- (ix86_function_specific_print): Assert arch and tune <
- PROCESSOR_max. Use processor_target_table to print arch and
- tune names.
+ (ix86_function_specific_print): Assert arch and tune < PROCESSOR_max.
+ Use processor_target_table to print arch and tune names.
* config/i386/i386.h (TARGET_CPU_DEFAULT): Default to
PROCESSOR_GENERIC.
(target_cpu_default): Removed.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 4d0b264..e02d05d 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -126,6 +126,18 @@ decode_caches_intel (unsigned reg, bool xeon_mp,
case 0x0c:
level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
break;
+ case 0x0d:
+ level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
+ break;
+ case 0x0e:
+ level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
+ break;
+ case 0x21:
+ level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
+ break;
+ case 0x24:
+ level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
+ break;
case 0x2c:
level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
break;
@@ -162,6 +174,9 @@ decode_caches_intel (unsigned reg, bool xeon_mp,
case 0x45:
level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
break;
+ case 0x48:
+ level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
+ break;
case 0x49:
if (xeon_mp)
break;
@@ -203,6 +218,9 @@ decode_caches_intel (unsigned reg, bool xeon_mp,
case 0x7f:
level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
break;
+ case 0x80:
+ level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
+ break;
case 0x82:
level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
break;