re PR target/46153 (ICE: in extract_insn, at recog.c:2110 (unrecognizable insn) with -ffloat-store and __builtin_ia32_movlhps)

	PR target/46153
	* config/i386/sse.md (sse_movhlps_exp): Use destination
	returned from ix86_fixup_binary_operands to expand insn.
	(sse_movlhps_exp): Ditto.
	(sse_loadhps_exp): Ditto.
	(sse_loadlps_exp): Ditto.
	(sse2_loadhpd_exp): Ditto.
	(sse2_loadlpd_exp): Ditto.
	(*avx_movhlps): Use ix86_binary_operator_ok in insn predicate.
	(sse_movhlps): Ditto.
	(*avx_movlhps): Ditto.
	(sse_movlhps): Ditto.
	(*avx_loadhps): Ditto.
	(sse_loadhps): Ditto.
	(*avx_loadhpd): Ditto.
	(sse_loadhpd): Ditto.
	(*avx_storelps): Prevent both operands in memory.
	(sse_storelps): Ditto.

testsuite/ChangeLog:

	PR target/46153
	* gcc.target/i386/pr46153.c: New test.

From-SVN: r166031

4 files changed, 148 insertions, 61 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bcdb1c2..3a6a557 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,24 @@
+2010-10-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/46153
+	* config/i386/sse.md (sse_movhlps_exp): Use destination
+	returned from ix86_fixup_binary_operands to expand insn.
+	(sse_movlhps_exp): Ditto.
+	(sse_loadhps_exp): Ditto.
+	(sse_loadlps_exp): Ditto.
+	(sse2_loadhpd_exp): Ditto.
+	(sse2_loadlpd_exp): Ditto.
+	(*avx_movhlps): Use ix86_binary_operator_ok in insn predicate.
+	(sse_movhlps): Ditto.
+	(*avx_movlhps): Ditto.
+	(sse_movlhps): Ditto.
+	(*avx_loadhps): Ditto.
+	(sse_loadhps): Ditto.
+	(*avx_loadhpd): Ditto.
+	(sse_loadhpd): Ditto.
+	(*avx_storelps): Prevent both operands in memory.
+	(sse_storelps): Ditto.
+
 2010-10-28  Andrew Stubbs  <ams@codesourcery.com>
 
 	* config/arm/arm.c (const_ok_for_arm): Support 0xXY00XY00 pattern
@@ -104,8 +125,7 @@
 	caller_pass_avx256_p based on argument type.
 	(ix86_expand_epilogue): Emit vzeroupper if 256bit AVX register
 	is used, but not returned by caller.
-	(ix86_expand_call): Emit vzeroupper if 256bit AVX register is
-	used.
+	(ix86_expand_call): Emit vzeroupper if 256bit AVX register is used.
 	(ix86_local_alignment): Set use_avx256_p if 256bit AVX register
 	is used.
 	(ix86_minimum_alignment): Likewise.
@@ -136,7 +156,7 @@
 	* config/i386/t-mingw-w64 (SHLIB_LC): Likewise.
 
 2010-10-27  Eric Botcazou  <ebotcazou@adacore.com>
-            Olivier Hainque  <hainque@adacore.com>
+	    Olivier Hainque  <hainque@adacore.com>
 
 	* config/i386/w32-unwind.h (i386_w32_fallback_frame_state): Fix regnum
 	of EBP.  Do not restore reg #9.  Remove +1 adjustment to EIP and set
@@ -165,11 +185,10 @@
 	c_parser_objc_at_property, now
 	c_parser_objc_at_property_declaration.
 	(c_parser_objc_methodprotolist): Same change.
-	
+
 2010-10-26  H.J. Lu  <hongjiu.lu@intel.com>
 
-	* config/i386/i386.md (split_stack_return): Put back
-	unspec_volatile.
+	* config/i386/i386.md (split_stack_return): Put back unspec_volatile.
 
 2010-10-26  Jan Hubicka  <jh@suse.cz>
 
@@ -180,7 +199,8 @@
 
 2010-10-26  Jan Hubicka  <jh@suse.cz>
 
-	* cgraphbuild.c (build_cgraph_edges): Use ipa-reference to represent OMP.
+	* cgraphbuild.c (build_cgraph_edges): Use ipa-reference
+	to represent OMP.
 
 2010-10-26  H.J. Lu  <hongjiu.lu@intel.com>
 
@@ -213,31 +233,33 @@
 	(cgraph_can_remove_if_no_direct_calls_and_refs): Do not try
 	to optimize away static ctors/dtors; it does not work on inline clones;
 	external functions can always be rmeoved.
-	(cgraph_will_be_removed_from_program_if_no_direct_calls): Assert on inline
-	clones; in LTO external functions always can go.
+	(cgraph_will_be_removed_from_program_if_no_direct_calls): Assert on
+	inline clones; in LTO external functions always can go.
 	(cgraph_used_from_object_file_p): Handle EXTERNAL functions correctly.
-	(cgraph_mark_address_taken_node): Assert that we are not taking address of
-	inline clone.
+	(cgraph_mark_address_taken_node): Assert that we are not taking
+	address of inline clone.
 	(cgraph_can_remove_if_no_direct_calls_p): We always eventually remove
 	external functions.
-	* ipa-cp.c (ipcp_cloning_candidate_p): Do not clone functions with address taken.
-	(ipcp_initialize_node_lattices): Only local functions can be handled without cloning.
+	* ipa-cp.c (ipcp_cloning_candidate_p): Do not clone functions with
+	address taken.
+	(ipcp_initialize_node_lattices): Only local functions can be
+	handled without cloning.
 	* cgraph.h (cgraph_set_readonly_flag,
 	cgraph_set_looping_const_or_pure_flag): Remove.
 	(cgraph_set_const_flag): Declare.
 	(cgraph_set_pure_flag): Update.
 	* ipa-pure-const (propagate_pure_const, local_pure_const): Update
 	flags setting code.
-	* ipa.c (cgraph_remove_unreachable_nodes): Fix formating; do not look at inline
-	clones; fix handling of external definitions.
+	* ipa.c (cgraph_remove_unreachable_nodes): Fix formating; do not
+	look at inline clones; fix handling of external definitions.
 	(cgraph_postorder): Do not look at inline clones in the first pass.
 	(function_and_variable_visibility): Drop constructors/destructor
 	flags at pure and const functions.
 	* tree-profile.c (tree_profiling): Update.
 	* ipa-inline.c (cgraph_clone_inlined_nodes): Always clone functions with
 	address taken; external functions do not account to whole program size.
-	(cgraph_decide_inlining): Likewise; do not try to inline functions already
-	inlined.
+	(cgraph_decide_inlining): Likewise; do not try to inline
+	functions already inlined.
 
 2010-10-26  Jie Zhang  <jie@codesourcery.com>
 
@@ -260,7 +282,7 @@
 	PR target/44948
 	* config/i386/i386.c (ix86_old_function_arg_boundary): New.
 	(ix86_function_arg_boundary): Always align parameters on stack
-	in 64bit and align parameters with alignment >= 16byte on stack 
+	in 64bit and align parameters with alignment >= 16byte on stack
 	in 32bit.  Warn alignment change.
 
 2010-10-26  Ian Lance Taylor  <iant@google.com>
@@ -269,7 +291,7 @@
 	* ipa-prop.c (ipa_modify_call_arguments): Correct type of MEM_REF
 	offset.
 
-2010-10-25  Rodrigo Rivas Costa <rodrigorivascosta@gmail.com>
+2010-10-25  Rodrigo Rivas Costa  <rodrigorivascosta@gmail.com>
 
 	Implement opaque-enum-specifiesr for C++0x
 	* tree.h (ENUM_IS_OPAQUE): New.
@@ -278,8 +300,7 @@
 2010-10-26  Jie Zhang  <jie@codesourcery.com>
 
 	* stor-layout.c (layout_decl): Use the field's type to
-	determine the mode and keep DECL_BIT_FIELD for a volatile
-	bit-field.
+	determine the mode and keep DECL_BIT_FIELD for a volatile bit-field.
 	* config/arm/arm.c (arm_override_options): Default to
 	-fstrict-volatile-bitfields.
 
@@ -290,10 +311,6 @@
 	* config/pdp11/pdp11.c: Use named constants instead of numbers.
 	* config/pdp11.pdp11.h: Ditto.
 
-2010-10-25  Changpeng Fang  <changpeng.fang@amd.com>
-
-	* Changelog (2010-10-22  Changpeng Fang): Correct the Changelog entries.
-
 2010-10-25  Eric Botcazou  <ebotcazou@adacore.com>
 
 	* configure.ac: Use $cpu_type instead of $target to define the nop.
@@ -323,8 +340,7 @@
 
 2010-10-24  Ian Lance Taylor  <iant@google.com>
 
-	* config/i386/i386.c (ix86_va_start): Remove extraneous blank
-	line.
+	* config/i386/i386.c (ix86_va_start): Remove extraneous blank line.
 
 2010-10-24  Eric Botcazou  <ebotcazou@adacore.com>
 
@@ -338,8 +354,7 @@
 	* gcc.c (n_switches_alloc_debug_check): New.
 	(set_option_handlers): New.
 	(process_command): Use set_option_handlers.
-	(do_self_spec): Pass spec-generated options through option
-	handlers.
+	(do_self_spec): Pass spec-generated options through option handlers.
 	(main): Also save and restore n_switches_alloc when swapping
 	switch arrays.
 
@@ -399,7 +414,7 @@
 	(TARGET_SCHED_REORDER2): Define to mips_sched_reorder2
 	instead of mips_sched_reorder.
 
-	Revert
+	Revert:
 	2008-09-09  Andrey Belevantsev  <abel@ispras.ru>
 	PR rtl-optimization/37360
 	* haifa-sched.c (max_issue): Do not assert that we never issue more
@@ -432,8 +447,7 @@
 	(m32c_addr_space_subset_p): New.
 	(m32c_addr_space_convert): New.
 	(conversions): Add __far operand patterns.
-	(m32c_prepare_move): Force constants into registers for __far
-	moves.
+	(m32c_prepare_move): Force constants into registers for __far moves.
 	(m32c_split_move): __far moves are always split.
 	* config/m32c/addsub.md (addsi3_1): Support SImode symbols.
 	* config/m32c/mov.md (mov<mode>_far_op1): New.
@@ -442,8 +456,8 @@
 	(movhi_op): Likewise.
 	(movsi_splittable): Split A1A0 also.
 
-2010-10-22  Artjoms Sinkarovs <artyom.shinakroff@gmail.com>
-	    Andrew Pinski <pinskia@gmail.com>
+2010-10-22  Artjoms Sinkarovs  <artyom.shinakroff@gmail.com>
+	    Andrew Pinski  <pinskia@gmail.com>
 
 	* c-typeck.c (build_array_ref): Handle subscripting of vectors.
 	* doc/extend.texi: New paragraph
@@ -476,8 +490,7 @@
 
 	* gcc.c (DEFAULT_SWITCH_CURTAILS_COMPILATION,
 	SWITCH_CURTAILS_COMPILATION): Remove.
-	* doc/tm.texi.in (SWITCH_CURTAILS_COMPILATION): Remove
-	documentation.
+	* doc/tm.texi.in (SWITCH_CURTAILS_COMPILATION): Remove documentation.
 	* doc/tm.texi: Regenerate.
 	* system.h (SWITCH_CURTAILS_COMPILATION): Poison.
 
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 078fac6..eefa745 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3244,7 +3244,17 @@
 		     (const_int 2)
 		     (const_int 3)])))]
   "TARGET_SSE"
-  "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
+{
+  rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
+  
+  emit_insn (gen_sse_movhlps (dst, operands[1], operands[2]));
+
+  /* Fix up the destination if needed.  */
+  if (dst != operands[0])
+    emit_move_insn (operands[0], dst);
+
+  DONE;
+})
 
 (define_insn "*avx_movhlps"
   [(set (match_operand:V4SF 0 "nonimmediate_operand"     "=x,x,m")
@@ -3256,7 +3266,7 @@
 		     (const_int 7)
 		     (const_int 2)
 		     (const_int 3)])))]
-  "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
   "@
    vmovhlps\t{%2, %1, %0|%0, %1, %2}
    vmovlps\t{%H2, %1, %0|%0, %1, %H2}
@@ -3275,7 +3285,7 @@
 		     (const_int 7)
 		     (const_int 2)
 		     (const_int 3)])))]
-  "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
   "@
    movhlps\t{%2, %0|%0, %2}
    movlps\t{%H2, %0|%0, %H2}
@@ -3294,7 +3304,17 @@
 		     (const_int 4)
 		     (const_int 5)])))]
   "TARGET_SSE"
-  "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
+{
+  rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
+  
+  emit_insn (gen_sse_movlhps (dst, operands[1], operands[2]));
+
+  /* Fix up the destination if needed.  */
+  if (dst != operands[0])
+    emit_move_insn (operands[0], dst);
+
+  DONE;
+})
 
 (define_insn "*avx_movlhps"
   [(set (match_operand:V4SF 0 "nonimmediate_operand"     "=x,x,o")
@@ -3701,7 +3721,17 @@
 	    (parallel [(const_int 0) (const_int 1)]))
 	  (match_operand:V2SF 2 "nonimmediate_operand" "")))]
   "TARGET_SSE"
-  "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
+{
+  rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
+  
+  emit_insn (gen_sse_loadhps (dst, operands[1], operands[2]));
+
+  /* Fix up the destination if needed.  */
+  if (dst != operands[0])
+    emit_move_insn (operands[0], dst);
+
+  DONE;
+})
 
 (define_insn "*avx_loadhps"
   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
@@ -3710,7 +3740,7 @@
 	    (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
 	    (parallel [(const_int 0) (const_int 1)]))
 	  (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
-  "TARGET_AVX"
+  "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
   "@
    vmovhps\t{%2, %1, %0|%0, %1, %2}
    vmovlhps\t{%2, %1, %0|%0, %1, %2}
@@ -3726,7 +3756,7 @@
 	    (match_operand:V4SF 1 "nonimmediate_operand" "0,0,0")
 	    (parallel [(const_int 0) (const_int 1)]))
 	  (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
-  "TARGET_SSE"
+  "TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
   "@
    movhps\t{%2, %0|%0, %2}
    movlhps\t{%2, %0|%0, %2}
@@ -3739,7 +3769,7 @@
 	(vec_select:V2SF
 	  (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
 	  (parallel [(const_int 0) (const_int 1)])))]
-  "TARGET_AVX"
+  "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
    vmovlps\t{%1, %0|%0, %1}
    vmovaps\t{%1, %0|%0, %1}
@@ -3753,7 +3783,7 @@
 	(vec_select:V2SF
 	  (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
 	  (parallel [(const_int 0) (const_int 1)])))]
-  "TARGET_SSE"
+  "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
    movlps\t{%1, %0|%0, %1}
    movaps\t{%1, %0|%0, %1}
@@ -3769,7 +3799,17 @@
 	    (match_operand:V4SF 1 "nonimmediate_operand" "")
 	    (parallel [(const_int 2) (const_int 3)]))))]
   "TARGET_SSE"
-  "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
+{
+  rtx dst = ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);
+  
+  emit_insn (gen_sse_loadlps (dst, operands[1], operands[2]));
+
+  /* Fix up the destination if needed.  */
+  if (dst != operands[0])
+    emit_move_insn (operands[0], dst);
+
+  DONE;
+})
 
 (define_insn "*avx_loadlps"
   [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
@@ -3778,7 +3818,7 @@
 	  (vec_select:V2SF
 	    (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
 	    (parallel [(const_int 2) (const_int 3)]))))]
-  "TARGET_AVX"
+  "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
   "@
    shufps\t{$0xe4, %1, %2, %0|%0, %2, %1, 0xe4}
    vmovlps\t{%2, %1, %0|%0, %1, %2}
@@ -3795,7 +3835,7 @@
 	  (vec_select:V2SF
 	    (match_operand:V4SF 1 "nonimmediate_operand" "x,0,0")
 	    (parallel [(const_int 2) (const_int 3)]))))]
-  "TARGET_SSE"
+  "TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
   "@
    shufps\t{$0xe4, %1, %0|%0, %1, 0xe4}
    movlps\t{%2, %0|%0, %2}
@@ -4898,7 +4938,17 @@
 	    (parallel [(const_int 0)]))
 	  (match_operand:DF 2 "nonimmediate_operand" "")))]
   "TARGET_SSE2"
-  "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
+{
+  rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
+  
+  emit_insn (gen_sse2_loadhpd (dst, operands[1], operands[2]));
+
+  /* Fix up the destination if needed.  */
+  if (dst != operands[0])
+    emit_move_insn (operands[0], dst);
+
+  DONE;
+})
 
 ;; Avoid combining registers from different units in a single alternative,
 ;; see comment above inline_secondary_memory_needed function in i386.c
@@ -4909,7 +4959,7 @@
 	    (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,0,0")
 	    (parallel [(const_int 0)]))
 	  (match_operand:DF 2 "nonimmediate_operand"     " m,x,x,*f,r")))]
-  "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
   "@
    vmovhpd\t{%2, %1, %0|%0, %1, %2}
    vunpcklpd\t{%2, %1, %0|%0, %1, %2}
@@ -4927,7 +4977,7 @@
 	    (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,x,0,0,0")
 	    (parallel [(const_int 0)]))
 	  (match_operand:DF 2 "nonimmediate_operand"     " m,x,0,x,*f,r")))]
-  "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "TARGET_SSE2 && ix86_binary_operator_ok (UNKNOWN, V2DFmode, operands)"
   "@
    movhpd\t{%2, %0|%0, %2}
    unpcklpd\t{%2, %0|%0, %2}
@@ -4957,7 +5007,17 @@
 	    (match_operand:V2DF 1 "nonimmediate_operand" "")
 	    (parallel [(const_int 1)]))))]
   "TARGET_SSE2"
-  "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
+{
+  rtx dst = ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);
+  
+  emit_insn (gen_sse2_loadlpd (dst, operands[1], operands[2]));
+
+  /* Fix up the destination if needed.  */
+  if (dst != operands[0])
+    emit_move_insn (operands[0], dst);
+
+  DONE;
+})
 
 ;; Avoid combining registers from different units in a single alternative,
 ;; see comment above inline_secondary_memory_needed function in i386.c
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a4811f2..b28c078 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2010-10-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	PR target/46153
+	* gcc.target/i386/pr46153.c: New test.
+
 2010-10-27  Jason Merrill  <jason@redhat.com>
 
 	* g++.dg/cpp0x/constexpr-is_literal.C: New.
@@ -33,16 +38,16 @@
 	updates in warning.
 	* obj-c++.dg/property/property-neg-5.mm: Updated testcase for
 	updates in warning.
-	
+
 2010-10-27  Nicola Pero  <nicola.pero@meta-innovation.com>
 
-	* objc.dg/property/at-property-1.m: New.	
+	* objc.dg/property/at-property-1.m: New.
 	* objc.dg/property/at-property-2.m: New.
 	* objc.dg/property/at-property-3.m: New.
 	* objc.dg/ivar-invalid-type-1.m: New.
 	* obj-c++.dg/property/at-property-1.mm: New.
 	* obj-c++.dg/property/at-property-2.mm: New.
-	* obj-c++.dg/property/at-property-3.mm: New.	
+	* obj-c++.dg/property/at-property-3.mm: New.
 	* obj-c++.dg/ivar-invalid-type-1.mm: New.
 	* objc.dg/property/property-neg-6.m: Updated testcase for updates
 	in error reporting.
@@ -172,8 +177,8 @@
 
 2010-10-24  Nicola Pero  <nicola.pero@meta-innovation.com>
 
-	PR objc/45735	
-	* obj-c.dg/pr45735.mm: New.	
+	PR objc/45735
+	* obj-c.dg/pr45735.mm: New.
 	* obj-c++.dg/pr45735.mm: New.
 
 2010-10-24  Nicola Pero  <nicola.pero@meta-innovation.com>
@@ -194,10 +199,10 @@
 	parameter attributes are now supported.
 	* obj-c++.dg/attributes/method-attribute-2.m: Same change.
 	* objc.dg/attributes/parameter-attribute-1.m: New test.
-	* objc.dg/attributes/parameter-attribute-2.m: New test.	
+	* objc.dg/attributes/parameter-attribute-2.m: New test.
 	* obj-c++.dg/attributes/parameter-attribute-1.m: New test.
-	* obj-c++.dg/attributes/parameter-attribute-2.m: New test.	
-	
+	* obj-c++.dg/attributes/parameter-attribute-2.m: New test.
+
 2010-10-23  Iain Sandoe  <iains@gcc.gnu.org>
 
 	Based on the CFString implementation in FSF apple/trunk branch.
@@ -213,7 +218,7 @@
 	* objc.dg/demangle-1.m: New test.
 	* obj-c++.dg/demangle-1.mm: New test.
 	* obj-c++.dg/demangle-2.mm: New test.
-	* obj-c++.dg/demangle-3.mm: New test.	
+	* obj-c++.dg/demangle-3.mm: New test.
 
 2010-10-23  Ian Lance Taylor  <iant@google.com>
 
diff --git a/gcc/testsuite/gcc.target/i386/pr46153.c b/gcc/testsuite/gcc.target/i386/pr46153.c
new file mode 100644
index 0000000..c6e0f52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr46153.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-msse -ffloat-store" } */
+
+typedef float v4sf __attribute__ ((__vector_size__ (16)));
+
+v4sf foo (v4sf a)
+{
+  return __builtin_ia32_movlhps (a, a);
+}