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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2015-03-26 04:07:21 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2015-03-26 04:07:21 +0000 |
| commit | ee8c0889cdc4960ac1f6fa9e1322291bb145cff6 (patch) | |
| tree | f8bca2f0543f3731835379de20cc574bf158e79f | |
| parent | 9c5b1bf7953f9717943e40241be26cfc2422cd04 (diff) | |
| download | gcc-ee8c0889cdc4960ac1f6fa9e1322291bb145cff6.zip gcc-ee8c0889cdc4960ac1f6fa9e1322291bb145cff6.tar.gz gcc-ee8c0889cdc4960ac1f6fa9e1322291bb145cff6.tar.bz2 | |
re PR target/65569 (Fix for PR target/65240 causes a regression in building Spec for power4/power5/power6)
2015-03-25 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/65569
* config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use
XXLXOR to create 0.0. On pre-VSX systems make sure the constant
0.0 is correctly setup.
(extenddftf2_internal): Likewise.
From-SVN: r221683
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 19 |
2 files changed, 20 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5e47d38..5733d90 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-03-25 Michael Meissner <meissner@linux.vnet.ibm.com> + + PR target/65569 + * config/rs6000/rs6000.md (extenddftf2_fprs): On VSX systems use + XXLXOR to create 0.0. On pre-VSX systems make sure the constant + 0.0 is correctly setup. + (extenddftf2_internal): Likewise. + 2015-03-25 Sebastian Pop <s.pop@samsung.com> PR tree-optimization/65177 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index aec696e..da96287 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8357,16 +8357,21 @@ && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" { - operands[2] = CONST0_RTX (DFmode); - /* Generate GOT reference early for SVR4 PIC. */ - if (DEFAULT_ABI == ABI_V4 && flag_pic) - operands[2] = validize_mem (force_const_mem (DFmode, operands[2])); + /* VSX can create 0.0 directly, otherwise let rs6000_emit_move create + the proper constant. */ + if (TARGET_VSX) + operands[2] = CONST0_RTX (DFmode); + else + { + operands[2] = gen_reg_rtx (DFmode); + rs6000_emit_move (operands[2], CONST0_RTX (DFmode), DFmode); + } }) (define_insn_and_split "*extenddftf2_internal" - [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r") - (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rm"))) - (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,ws,d,&d,r") + (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,md,rm"))) + (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,j,m,d,n"))] "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" |