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| author | Jim Wilson <wilson@gcc.gnu.org> | 1992-04-07 21:53:48 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1992-04-07 21:53:48 -0700 |
| commit | ea3fa5f72bb8726d9fb4f03aa8bcf59b263b2d71 (patch) | |
| tree | 557013ebe974f77065f29da081f86fc9b02d5b10 | |
| parent | 0be8e85950ca7f3732cbfa67271fc4b8ff56c418 (diff) | |
| download | gcc-ea3fa5f72bb8726d9fb4f03aa8bcf59b263b2d71.zip gcc-ea3fa5f72bb8726d9fb4f03aa8bcf59b263b2d71.tar.gz gcc-ea3fa5f72bb8726d9fb4f03aa8bcf59b263b2d71.tar.bz2 | |
*** empty log message ***
From-SVN: r708
| -rw-r--r-- | gcc/config/sparc/sparc.h | 9 | ||||
| -rw-r--r-- | gcc/sched.c | 7 |
2 files changed, 12 insertions, 4 deletions
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index b997b4a..10f7b0e 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -1378,6 +1378,15 @@ extern struct rtx_def *legitimize_pic_address (); "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"} +/* Define additional names for use in asm clobbers and asm declarations. + + We define the fake Condition Code register as an alias for reg 0 (which + is our `condition code' register), so that condition codes can easily + be clobbered by an asm. No such register actually exists. Condition + codes are partly stored in the PSR and partly in the FSR. */ + +#define ADDITIONAL_REGISTER_NAMES {"ccr", 0} + /* How to renumber registers for dbx and gdb. */ #define DBX_REGISTER_NUMBER(REGNO) (REGNO) diff --git a/gcc/sched.c b/gcc/sched.c index 0c3d6aa..93e6a07 100644 --- a/gcc/sched.c +++ b/gcc/sched.c @@ -1217,10 +1217,9 @@ sched_analyze_2 (x, insn) rtx link; /* User of CC0 depends on immediately preceding insn. - All notes are removed from the list of insns to schedule before we - reach here, so the previous insn must be the setter of cc0. */ - if (GET_CODE (PREV_INSN (insn)) != INSN) - abort (); + There may be a note before this insn now, but all notes will + be removed before we actually try to schedule the insns, so + it doesn't matter. */ SCHED_GROUP_P (insn) = 1; /* Make a copy of all dependencies on PREV_INSN, and add to this insn. |