diff options
| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:26:59 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:26:59 -0700 |
| commit | e8b0e9104f2663a0d65cd65e7c4bd25c0b10514b (patch) | |
| tree | 66def54d88f880b8c7eb735b11045e4e9c3462a6 | |
| parent | 16ed2601ad0a4aa82f11e9df86ea92183f94f979 (diff) | |
| download | gcc-e8b0e9104f2663a0d65cd65e7c4bd25c0b10514b.zip gcc-e8b0e9104f2663a0d65cd65e7c4bd25c0b10514b.tar.gz gcc-e8b0e9104f2663a0d65cd65e7c4bd25c0b10514b.tar.bz2 | |
i386: Emulate MMX ssse3_psign<mode>3 with SSE
Emulate MMX ssse3_psign<mode>3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation.
From-SVN: r271246
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 18 |
2 files changed, 16 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f702f8..406b879 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,11 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/sse.md (ssse3_psign<mode>3): Add SSE emulation. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/sse.md (ssse3_pshufbv8qi3): Changed to define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add SSE emulation. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9c2ca68..424faf8 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16233,17 +16233,21 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "ssse3_psign<mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (unspec:MMXMODEI - [(match_operand:MMXMODEI 1 "register_operand" "0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")] + [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")] UNSPEC_PSIGN))] - "TARGET_SSSE3" - "psign<mmxvecsize>\t{%2, %0|%0, %2}"; - [(set_attr "type" "sselog1") + "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" + "@ + psign<mmxvecsize>\t{%2, %0|%0, %2} + psign<mmxvecsize>\t{%2, %0|%0, %2} + vpsign<mmxvecsize>\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "sselog1") (set_attr "prefix_extra" "1") (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "<ssse3_avx2>_palignr<mode>_mask" [(set (match_operand:VI1_AVX512 0 "register_operand" "=v") |