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| author | Richard Henderson <rth@redhat.com> | 2004-12-23 02:32:42 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2004-12-23 02:32:42 -0800 |
| commit | e26b63b29fc9567f9eab418b05657bcc00a9eb0a (patch) | |
| tree | 1346086dc0a91c636109b0df10bb480426012e19 | |
| parent | 3e8aba3481e8d3f7a1a06695f3e479370643b130 (diff) | |
| download | gcc-e26b63b29fc9567f9eab418b05657bcc00a9eb0a.zip gcc-e26b63b29fc9567f9eab418b05657bcc00a9eb0a.tar.gz gcc-e26b63b29fc9567f9eab418b05657bcc00a9eb0a.tar.bz2 | |
alpha.md (one_cmpl<mode>2, [...]): New macroized vector operate patterns.
* config/alpha/alpha.md (one_cmpl<mode>2, and<mode>3, andnot<mode>3,
ior<mode>3, iornot<mode>3, xor<mode>3, xornot<mode>3): New macroized
vector operate patterns.
From-SVN: r92545
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 55 |
2 files changed, 61 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 1fa3c95..3ddbf23 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2004-12-23 Richard Henderson <rth@redhat.com> + * config/alpha/alpha.md (one_cmpl<mode>2, and<mode>3, andnot<mode>3, + ior<mode>3, iornot<mode>3, xor<mode>3, xornot<mode>3): New macroized + vector operate patterns. + +2004-12-23 Richard Henderson <rth@redhat.com> + * config/i386/i386.c (ix86_expand_vector_move): Tidy. (ix86_expand_vector_move_misalign): New. (ix86_misaligned_mem_ok): Remove. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 145e23c..2679324 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -6207,6 +6207,61 @@ "TARGET_MAX" "maxsw4 %r1,%r2,%0" [(set_attr "type" "mvi")]) + +(define_insn "one_cmpl<mode>2" + [(set (match_operand:VEC 0 "register_operand" "=r") + (not:VEC (match_operand:VEC 1 "register_operand" "r")))] + "" + "ornot $31,%1,%0" + [(set_attr "type" "ilog")]) + +(define_insn "and<mode>3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (and:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r")))] + "" + "and %1,%2,%0" + [(set_attr "type" "ilog")]) + +(define_insn "*andnot<mode>3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) + (match_operand:VEC 2 "register_operand" "r")))] + "" + "bic %2,%1,%0" + [(set_attr "type" "ilog")]) + +(define_insn "ior<mode>3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (ior:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r")))] + "" + "bis %1,%2,%0" + [(set_attr "type" "ilog")]) + +(define_insn "*iornot<mode>3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) + (match_operand:VEC 2 "register_operand" "r")))] + "" + "ornot %2,%1,%0" + [(set_attr "type" "ilog")]) + +(define_insn "xor<mode>3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (xor:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r")))] + "" + "xor %1,%2,%0" + [(set_attr "type" "ilog")]) + +(define_insn "*xornot<mode>3" + [(set (match_operand:VEC 0 "register_operand" "=r") + (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") + (match_operand:VEC 2 "register_operand" "r"))))] + "" + "eqv %1,%2,%0" + [(set_attr "type" "ilog")]) ;; Bit field extract patterns which use ext[wlq][lh] |