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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:09:50 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:09:50 -0700 |
| commit | df0e1979a8f5f0d3bdaff06393cf1bddfd725e6d (patch) | |
| tree | d89984c592c79d9289b2aefcfb350cfa21977b56 | |
| parent | fff6304f52e3dc48b2e26683e1260fda977cbd86 (diff) | |
| download | gcc-df0e1979a8f5f0d3bdaff06393cf1bddfd725e6d.zip gcc-df0e1979a8f5f0d3bdaff06393cf1bddfd725e6d.tar.gz gcc-df0e1979a8f5f0d3bdaff06393cf1bddfd725e6d.tar.bz2 | |
i386: Emulate MMX mmx_andnot<mode>3 with SSE
Emulate MMX mmx_andnot<mode>3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot<mode>3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
From-SVN: r271223
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 18 |
2 files changed, 17 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7bee150..12ab4d0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,12 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_andnot<mode>3): Also allow + TARGET_MMX_WITH_SSE. Add SSE support. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (any_logic:mmx_<code><mode>3): Also allow TARGET_MMX_WITH_SSE. (any_logic:<code><mode>3): New. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 058d805..d3201d8 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1074,14 +1074,18 @@ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (define_insn "mmx_andnot<mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") (and:MMXMODEI - (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0")) - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX" - "pandn\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) + (not:MMXMODEI (match_operand:MMXMODEI 1 "register_operand" "0,0,Yv")) + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")))] + "TARGET_MMX || TARGET_MMX_WITH_SSE" + "@ + pandn\t{%2, %0|%0, %2} + pandn\t{%2, %0|%0, %2} + vpandn\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxadd,sselog,sselog") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_<code><mode>3" [(set (match_operand:MMXMODEI 0 "register_operand") |