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authorJakub Jelinek <jakub@redhat.com>2017-11-08 21:15:42 +0100
committerJakub Jelinek <jakub@gcc.gnu.org>2017-11-08 21:15:42 +0100
commitdeef5083cda7b805977fe537f05b23da9406894e (patch)
tree675b400724503bc35e7124ea30d995303b474f4b
parent7692ce17a3383c956400a55af88d4ff500dd614a (diff)
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re PR target/82855 (AVX512: replace OP+movemask with OP_mask+ktest)
PR target/82855 * config/i386/sse.md (<avx512>_eq<mode>3<mask_scalar_merge_name>, <avx512>_eq<mode>3<mask_scalar_merge_name>_1): Use nonimmediate_operand predicate for operand 1 instead of register_operand. From-SVN: r254552
-rw-r--r--gcc/ChangeLog8
-rw-r--r--gcc/config/i386/sse.md8
2 files changed, 12 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 805625f..15bba02 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2017-11-08 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/82855
+ * config/i386/sse.md (<avx512>_eq<mode>3<mask_scalar_merge_name>,
+ <avx512>_eq<mode>3<mask_scalar_merge_name>_1): Use
+ nonimmediate_operand predicate for operand 1 instead of
+ register_operand.
+
2017-11-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (store_pair_lanes<mode>):
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 200aad6..919b6c6 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -11127,7 +11127,7 @@
(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand")
(unspec:<avx512fmaskmode>
- [(match_operand:VI12_AVX512VL 1 "register_operand")
+ [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand")
(match_operand:VI12_AVX512VL 2 "nonimmediate_operand")]
UNSPEC_MASKED_EQ))]
"TARGET_AVX512BW"
@@ -11136,7 +11136,7 @@
(define_expand "<avx512>_eq<mode>3<mask_scalar_merge_name>"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand")
(unspec:<avx512fmaskmode>
- [(match_operand:VI48_AVX512VL 1 "register_operand")
+ [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand")]
UNSPEC_MASKED_EQ))]
"TARGET_AVX512F"
@@ -11145,7 +11145,7 @@
(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
(unspec:<avx512fmaskmode>
- [(match_operand:VI12_AVX512VL 1 "register_operand" "%v")
+ [(match_operand:VI12_AVX512VL 1 "nonimmediate_operand" "%v")
(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")]
UNSPEC_MASKED_EQ))]
"TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -11158,7 +11158,7 @@
(define_insn "<avx512>_eq<mode>3<mask_scalar_merge_name>_1"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
(unspec:<avx512fmaskmode>
- [(match_operand:VI48_AVX512VL 1 "register_operand" "%v")
+ [(match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")]
UNSPEC_MASKED_EQ))]
"TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"