Merge ashlsi3 and ashldi3

From-SVN: r211877

2 files changed, 51 insertions, 134 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e971717..89ac3b6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,13 @@
 2014-06-22  Segher Boessenkool  <segher@kernel.crashing.org>
 
+	* config/rs6000/rs6000.md (ashlsi3, two anonymous define_insns
+	and define_splits, ashldi3, *ashldi3_internal1, *ashldi3_internal2
+	and split, *ashldi3_internal3 and split): Delete, merge into...
+	(ashl<mode>3, ashl<mode>3_dot, ashl<mode>3_dot2): New.
+	(*ashlsi3_64): Fix formatting.  Replace "i" by "n".
+
+2014-06-22  Segher Boessenkool  <segher@kernel.crashing.org>
+
 	* config/rs6000/rs6000.md ("hH"): New define_mode_attr.
 	(lshrsi3, two anonymous define_insns and define_splits,
 	lshrdi3, *lshrdi3_internal1, *lshrdi3_internal2 and split,
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index af3586d..f8aca89 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4382,22 +4382,23 @@
 		    (const_int 0)))]
   "")
 
-(define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
+
+(define_insn "ashl<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+	(ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
+		    (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))]
   ""
   "@
-   slw %0,%1,%2
-   slwi %0,%1,%h2"
+   sl<wd> %0,%1,%2
+   sl<wd>i %0,%1,%<hH>2"
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
 (define_insn "*ashlsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-  	(zero_extend:DI
+	(zero_extend:DI
 	    (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
-		       (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
+		       (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))]
   "TARGET_POWERPC64"
   "@
    slw %0,%1,%2
@@ -4405,69 +4406,58 @@
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no")])
 
-(define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
+(define_insn_and_split "*ashl<mode>3_dot"
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+	(compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
+				(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
-  "TARGET_32BIT"
+   (clobber (match_scratch:GPR 0 "=r,r,r,r"))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   slw. %3,%1,%2
-   slwi. %3,%1,%h2
+   sl<wd>. %0,%1,%2
+   sl<wd>i. %0,%1,%<hH>2
    #
    #"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(ashift:GPR (match_dup 1)
+		    (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 3)
-	(ashift:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn ""
+(define_insn_and_split "*ashl<mode>3_dot2"
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
+	(compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")
+				(match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashift:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT"
+   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
+	(ashift:GPR (match_dup 1)
+		    (match_dup 2)))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   slw. %0,%1,%2
-   slwi. %0,%1,%h2
+   sl<wd>. %0,%1,%2
+   sl<wd>i. %0,%1,%<hH>2
    #
    #"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(ashift:GPR (match_dup 1)
+		    (match_dup 2)))
+   (set (match_dup 3)
+	(compare:CC (match_dup 0)
+		    (const_int 0)))]
+  ""
   [(set_attr "type" "shift")
    (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
    (set_attr "length" "4,4,8,8")])
 
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-	(ashift:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0)
-	(ashift:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
 
 (define_insn "rlwinm"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -5026,6 +5016,7 @@
 		    (const_int 0)))]
   "")
 
+
 (define_insn "ashrsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
@@ -7654,88 +7645,6 @@
 		    (const_int 0)))]
   "")
 
-(define_expand "ashldi3"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
-		   (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  "TARGET_POWERPC64"
-  "")
-
-(define_insn "*ashldi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
-		   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
-  "TARGET_POWERPC64"
-  "@
-   sld %0,%1,%2
-   sldi %0,%1,%H2"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no")])
-
-(define_insn "*ashldi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r,r,r"))]
-  "TARGET_64BIT"
-  "@
-   sld. %3,%1,%2
-   sldi. %3,%1,%H2
-   #
-   #"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no,yes,no")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3)
-	(ashift:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0)
-	(compare:CC (match_dup 3)
-		    (const_int 0)))]
-  "")
-
-(define_insn "*ashldi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
-			       (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
-	(ashift:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT"
-  "@
-   sld. %0,%1,%2
-   sldi. %0,%1,%H2
-   #
-   #"
-  [(set_attr "type" "shift")
-   (set_attr "var_shift" "yes,no,yes,no")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,4,8,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
-	(compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
-			       (match_operand:SI 2 "reg_or_cint_operand" ""))
-		    (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-	(ashift:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0)
-	(ashift:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 3)
-	(compare:CC (match_dup 0)
-		    (const_int 0)))]
-  "")
-
 (define_insn "*ashldi3_internal4"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")