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| author | Vladimir Makarov <vmakarov@redhat.com> | 2004-06-10 21:06:07 +0000 |
|---|---|---|
| committer | Vladimir Makarov <vmakarov@gcc.gnu.org> | 2004-06-10 21:06:07 +0000 |
| commit | d57f1617211f3309887c6ee18fca97ea7029ebc7 (patch) | |
| tree | 82e7ddb63b466a4273220496cb85c8b9ec5c360e | |
| parent | 322afd16ae583cc9c71d4177ce8318307a7a568a (diff) | |
| download | gcc-d57f1617211f3309887c6ee18fca97ea7029ebc7.zip gcc-d57f1617211f3309887c6ee18fca97ea7029ebc7.tar.gz gcc-d57f1617211f3309887c6ee18fca97ea7029ebc7.tar.bz2 | |
re PR target/15653 (Gcc 3.4 ICE on valid code)
2004-06-10 Vladimir Makarov <vmakarov@redhat.com>
PR target/15653
* haifa-sched.c (schedule_block): Finish cycle after issuing asm
insn.
From-SVN: r82942
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/haifa-sched.c | 11 |
2 files changed, 14 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7bd6609..6a1b4db 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2004-06-10 Vladimir Makarov <vmakarov@redhat.com> + + PR target/15653 + * haifa-sched.c (schedule_block): Finish cycle after issuing asm + insn. + 2004-06-10 Volker Reichelt <reichelt@igpm.rwth-aachen.de> PR web/15263 diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c index af8b8a7..033aaae 100644 --- a/gcc/haifa-sched.c +++ b/gcc/haifa-sched.c @@ -2378,6 +2378,7 @@ schedule_block (int b, int rgn_n_insns) { rtx insn; int cost; + bool asm_p = false; if (sched_verbose >= 2) { @@ -2435,9 +2436,9 @@ schedule_block (int b, int rgn_n_insns) memcpy (temp_state, curr_state, dfa_state_size); if (recog_memoized (insn) < 0) { - if (!first_cycle_insn_p - && (GET_CODE (PATTERN (insn)) == ASM_INPUT - || asm_noperands (PATTERN (insn)) >= 0)) + asm_p = (GET_CODE (PATTERN (insn)) == ASM_INPUT + || asm_noperands (PATTERN (insn)) >= 0); + if (!first_cycle_insn_p && asm_p) /* This is asm insn which is tryed to be issued on the cycle not first. Issue it on the next cycle. */ cost = 1; @@ -2552,6 +2553,10 @@ schedule_block (int b, int rgn_n_insns) can_issue_more--; advance = schedule_insn (insn, &ready, clock_var); + + /* After issuing an asm insn we should start a new cycle. */ + if (advance == 0 && asm_p) + advance = 1; if (advance != 0) break; |