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| author | Doug Evans <devans@canuck.cygnus.com> | 1997-11-11 00:39:39 +0000 |
|---|---|---|
| committer | Doug Evans <devans@gcc.gnu.org> | 1997-11-11 00:39:39 +0000 |
| commit | d1f4474e5eadc1f3d54b5c95824c2d7e1b620af3 (patch) | |
| tree | 1a41cb26e073bb7b96185620b72bd191860724d0 | |
| parent | c7ae64f2cc5733e40bfb3ca6a58a63ece97691e3 (diff) | |
| download | gcc-d1f4474e5eadc1f3d54b5c95824c2d7e1b620af3.zip gcc-d1f4474e5eadc1f3d54b5c95824c2d7e1b620af3.tar.gz gcc-d1f4474e5eadc1f3d54b5c95824c2d7e1b620af3.tar.bz2 | |
sparc.md (mov[sdt]f_const_insn): Fix condition to match what the instruction can handle.
* sparc/sparc.md (mov[sdt]f_const_insn): Fix condition to match
what the instruction can handle.
From-SVN: r16422
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/sparc/sparc.md | 15 |
2 files changed, 17 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3322230..b0b82d9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +Mon Nov 10 16:21:58 1997 Doug Evans <devans@canuck.cygnus.com> + + * sparc/sparc.md (mov[sdt]f_const_insn): Fix condition to match + what the instruction can handle. + Mon Nov 10 03:02:19 1997 Jason Merrill <jason@yorick.cygnus.com> * stmt.c (expand_decl_cleanup_no_eh): New fn. diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index b1afbcd..8ec12f5 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -2157,7 +2157,10 @@ (define_insn "*movsf_const_insn" [(set (match_operand:SF 0 "general_operand" "=?r,f,m") (match_operand:SF 1 "" "?F,m,G"))] - "TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE" + "TARGET_FPU + && GET_CODE (operands[1]) == CONST_DOUBLE + && (GET_CODE (operands[0]) == REG + || fp_zero_operand (operands[1]))" "* { switch (which_alternative) @@ -2231,7 +2234,10 @@ (define_insn "*movdf_const_insn" [(set (match_operand:DF 0 "general_operand" "=?r,e,o") (match_operand:DF 1 "" "?F,m,G"))] - "TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE" + "TARGET_FPU + && GET_CODE (operands[1]) == CONST_DOUBLE + && (GET_CODE (operands[0]) == REG + || fp_zero_operand (operands[1]))" "* { switch (which_alternative) @@ -2349,7 +2355,10 @@ (define_insn "*movtf_const_insn" [(set (match_operand:TF 0 "general_operand" "=?r,e,o") (match_operand:TF 1 "" "?F,m,G"))] - "TARGET_FPU && GET_CODE (operands[1]) == CONST_DOUBLE" + "TARGET_FPU + && GET_CODE (operands[1]) == CONST_DOUBLE + && (GET_CODE (operands[0]) == REG + || fp_zero_operand (operands[1]))" "* { switch (which_alternative) |