mep-ivc2.cpu (cpmovtocsar0_C3, [...]): Mark volatile.

* config/mep/mep-ivc2.cpu (cpmovtocsar0_C3, cpmovtocsar1_C3,
cpmovtocc_C3, cpmovtocsar0_P0S_P1, cpmovtocsar1_P0S_P1,
cpmovtocc_P0S_P1): Mark volatile.  Note which registers are
written to.
* config/mep/intrinsics.md: Regenerated.
* config/mep/mep.c (mep_interrupt_saved_reg): Save IVC2 control
registers when asm() or calls are detected.

From-SVN: r149361

4 files changed, 55 insertions, 30 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 60d0e7e..fe86f87 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2009-07-08  DJ Delorie  <dj@redhat.com>
+
+	* config/mep/mep-ivc2.cpu (cpmovtocsar0_C3, cpmovtocsar1_C3,
+	cpmovtocc_C3, cpmovtocsar0_P0S_P1, cpmovtocsar1_P0S_P1,
+	cpmovtocc_P0S_P1): Mark volatile.  Note which registers are
+	written to.
+	* config/mep/intrinsics.md: Regenerated.
+	* config/mep/mep.c (mep_interrupt_saved_reg): Save IVC2 control
+	registers when asm() or calls are detected.
+	
 2009-07-08  Manuel López-Ibáñez  <manu@gcc.gnu.org>
 
 	PR c++/31246
diff --git a/gcc/config/mep/intrinsics.md b/gcc/config/mep/intrinsics.md
index 76a19c9..44343d3 100644
--- a/gcc/config/mep/intrinsics.md
+++ b/gcc/config/mep/intrinsics.md
@@ -15862,9 +15862,10 @@
 
 
 (define_insn "cgen_intrinsic_cpmovtocc_C3"
-  [(unspec_volatile [
-     (match_operand:DI 0 "general_operand" "x")
-   ] 3378)]
+  [(set (reg:SI 81)
+        (unspec_volatile:SI [
+          (match_operand:DI 0 "general_operand" "x")
+        ] 3378))]
   "CGEN_ENABLE_INSN_P (574)"
   "cpmovtocc\\t%0"
   [(set_attr "may_trap" "no")
@@ -15876,9 +15877,10 @@
 
 
 (define_insn "cgen_intrinsic_cpmovtocc_P0S_P1"
-  [(unspec_volatile [
-     (match_operand:DI 0 "general_operand" "x")
-   ] 3378)]
+  [(set (reg:SI 81)
+        (unspec_volatile:SI [
+          (match_operand:DI 0 "general_operand" "x")
+        ] 3378))]
   "CGEN_ENABLE_INSN_P (575)"
   "cpmovtocc\\t%0"
   [(set_attr "may_trap" "no")
@@ -15890,9 +15892,10 @@
 
 
 (define_insn "cgen_intrinsic_cpmovtocsar1_C3"
-  [(unspec_volatile [
-     (match_operand:DI 0 "general_operand" "x")
-   ] 3380)]
+  [(set (reg:SI 95)
+        (unspec_volatile:SI [
+          (match_operand:DI 0 "general_operand" "x")
+        ] 3380))]
   "CGEN_ENABLE_INSN_P (576)"
   "cpmovtocsar1\\t%0"
   [(set_attr "may_trap" "no")
@@ -15904,9 +15907,10 @@
 
 
 (define_insn "cgen_intrinsic_cpmovtocsar1_P0S_P1"
-  [(unspec_volatile [
-     (match_operand:DI 0 "general_operand" "x")
-   ] 3380)]
+  [(set (reg:SI 95)
+        (unspec_volatile:SI [
+          (match_operand:DI 0 "general_operand" "x")
+        ] 3380))]
   "CGEN_ENABLE_INSN_P (577)"
   "cpmovtocsar1\\t%0"
   [(set_attr "may_trap" "no")
@@ -15918,9 +15922,10 @@
 
 
 (define_insn "cgen_intrinsic_cpmovtocsar0_C3"
-  [(unspec_volatile [
-     (match_operand:DI 0 "general_operand" "x")
-   ] 3382)]
+  [(set (reg:SI 80)
+        (unspec_volatile:SI [
+          (match_operand:DI 0 "general_operand" "x")
+        ] 3382))]
   "CGEN_ENABLE_INSN_P (578)"
   "cpmovtocsar0\\t%0"
   [(set_attr "may_trap" "no")
@@ -15932,9 +15937,10 @@
 
 
 (define_insn "cgen_intrinsic_cpmovtocsar0_P0S_P1"
-  [(unspec_volatile [
-     (match_operand:DI 0 "general_operand" "x")
-   ] 3382)]
+  [(set (reg:SI 80)
+        (unspec_volatile:SI [
+          (match_operand:DI 0 "general_operand" "x")
+        ] 3382))]
   "CGEN_ENABLE_INSN_P (579)"
   "cpmovtocsar0\\t%0"
   [(set_attr "may_trap" "no")
diff --git a/gcc/config/mep/mep-ivc2.cpu b/gcc/config/mep/mep-ivc2.cpu
index ebb4938..1e00251 100644
--- a/gcc/config/mep/mep-ivc2.cpu
+++ b/gcc/config/mep/mep-ivc2.cpu
@@ -1463,36 +1463,39 @@
 
 ; 1111 0000 0000 0111 10000 qqqqq 10000 0   cpmovtocsar0 crqc (c3_1)
 (dni cpmovtocsar0_C3 "cpmovtocsar0 $crqc C3"
-  (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar0"))
+  (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar0") VOLATILE)
   "cpmovtocsar0 $crqc"
   (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
 	(f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) )
   (sequence ()
 	(c-call "check_option_cp" pc)
+	(set ivc2_csar0 0)
 	(c-call "ivc2_cpmovtocsar0" pc crqc) )
   ()
   )
 
 ; 1111 0000 0000 0111 10000 qqqqq 11111 0   cpmovtocsar1 crqc (c3_1)
 (dni cpmovtocsar1_C3 "cpmovtocsar1 $crqc C3"
-  (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar1"))
+  (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocsar1") VOLATILE)
   "cpmovtocsar1 $crqc"
   (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
 	(f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) )
   (sequence ()
 	(c-call "check_option_cp" pc)
+	(set ivc2_csar1 0)
 	(c-call "ivc2_cpmovtocsar1" pc crqc) )
   ()
   )
 
 ; 1111 0000 0000 0111 10000 qqqqq 10001 0   cpmovtocc crqc (c3_1)
 (dni cpmovtocc_C3 "cpmovtocc $crqc C3"
-  (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocc"))
+  (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovtocc") VOLATILE)
   "cpmovtocc $crqc"
   (+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
 	(f-ivc2-5u16 #x10) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) )
   (sequence ()
 	(c-call "check_option_cp" pc)
+	(set ivc2_cc 0)
 	(c-call "ivc2_cpmovtocc" pc crqc) )
   ()
   )
@@ -4948,33 +4951,36 @@
 
 ; 10001 qqqqq 10000 00000   cpmovtocsar0 crqp (p0_1)
 (dni cpmovtocsar0_P0S_P1 "cpmovtocsar0 $crqp Pn"
-  (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar0"))
+  (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar0") VOLATILE)
   "cpmovtocsar0 $crqp"
   (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
   (sequence ()
 	(c-call "check_option_cp" pc)
+	(set ivc2_csar0 0)
 	(c-call "ivc2_cpmovtocsar0" pc crqp) )
   ()
   )
 
 ; 10001 qqqqq 11111 00000   cpmovtocsar1 crqp (p0_1)
 (dni cpmovtocsar1_P0S_P1 "cpmovtocsar1 $crqp Pn"
-  (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar1"))
+  (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocsar1") VOLATILE)
   "cpmovtocsar1 $crqp"
   (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x1f) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
   (sequence ()
 	(c-call "check_option_cp" pc)
+	(set ivc2_csar1 0)
 	(c-call "ivc2_cpmovtocsar1" pc crqp) )
   ()
   )
 
 ; 10001 qqqqq 10001 00000   cpmovtocc crqp (p0_1)
 (dni cpmovtocc_P0S_P1 "cpmovtocc $crqp Pn"
-  (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocc"))
+  (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovtocc") VOLATILE)
   "cpmovtocc $crqp"
   (+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) crqp (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
   (sequence ()
 	(c-call "check_option_cp" pc)
+	(set ivc2_cc 0)
 	(c-call "ivc2_cpmovtocc" pc crqp) )
   ()
   )
diff --git a/gcc/config/mep/mep.c b/gcc/config/mep/mep.c
index 8a705ee..7237a03 100644
--- a/gcc/config/mep/mep.c
+++ b/gcc/config/mep/mep.c
@@ -2499,6 +2499,11 @@ mep_asm_without_operands_p (void)
    since they may get clobbered there too).  Here we check to see
    which call-used registers need saving.  */
 
+#define IVC2_ISAVED_REG(r) (TARGET_IVC2 \
+			   && (r == FIRST_CCR_REGNO + 1 \
+			       || (r >= FIRST_CCR_REGNO + 8 && r <= FIRST_CCR_REGNO + 11) \
+			       || (r >= FIRST_CCR_REGNO + 16 && r <= FIRST_CCR_REGNO + 31)))
+
 static bool
 mep_interrupt_saved_reg (int r)
 {
@@ -2509,11 +2514,12 @@ mep_interrupt_saved_reg (int r)
     return true;
   if (mep_asm_without_operands_p ()
       && (!fixed_regs[r]
-	  || (r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO || r == LP_REGNO)))
+	  || (r == RPB_REGNO || r == RPE_REGNO || r == RPC_REGNO || r == LP_REGNO)
+	  || IVC2_ISAVED_REG (r)))
     return true;
   if (!current_function_is_leaf)
     /* Function calls mean we need to save $lp.  */
-    if (r == LP_REGNO)
+    if (r == LP_REGNO || IVC2_ISAVED_REG (r))
       return true;
   if (!current_function_is_leaf || cfun->machine->doloop_tags > 0)
     /* The interrupt handler might use these registers for repeat blocks,
@@ -2526,10 +2532,7 @@ mep_interrupt_saved_reg (int r)
   if (call_used_regs[r] && !fixed_regs[r])
     return true;
   /* Additional registers that need to be saved for IVC2.  */
-  if (TARGET_IVC2
-      && (r == FIRST_CCR_REGNO + 1
-	  || (r >= FIRST_CCR_REGNO + 8 && r <= FIRST_CCR_REGNO + 11)
-	  || (r >= FIRST_CCR_REGNO + 16 && r <= FIRST_CCR_REGNO + 31)))
+  if (IVC2_ISAVED_REG (r))
     return true;
 
   return false;