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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-04-16 20:20:22 +0100 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2020-04-24 14:54:11 +0100 |
| commit | cf3a909cf45514cd294e483a7c86ef16c82ffa96 (patch) | |
| tree | 98a86b71aea62c4922728c591e0da7d15eda7a72 | |
| parent | 00082ff88cf4e25fc1041e9effd1c92fbaaa8d62 (diff) | |
| download | gcc-cf3a909cf45514cd294e483a7c86ef16c82ffa96.zip gcc-cf3a909cf45514cd294e483a7c86ef16c82ffa96.tar.gz gcc-cf3a909cf45514cd294e483a7c86ef16c82ffa96.tar.bz2 | |
amdgcn: Testsuite tweaks
The vector size chosen here is for V64DImode. The concept of this setting is
not well adapted for GCN, in which the vector size varies with the number of
lanes, not the other way around, but this is ok for now.
2020-04-24 Andrew Stubbs <ams@codesourcery.com>
gcc/testsuite/
* lib/target-supports.exp (available_vector_sizes): Add amdgcn.
(check_effective_target_vect_cmdline_needed): Disable for amdgcn.
(check_effective_target_vect_pack_trunc): Add amdgcn.
| -rw-r--r-- | gcc/testsuite/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 8 |
2 files changed, 12 insertions, 2 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 33edc25..ec14119 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2020-04-24 Andrew Stubbs <ams@codesourcery.com> + + * lib/target-supports.exp (available_vector_sizes): Add amdgcn. + (check_effective_target_vect_cmdline_needed): Disable for amdgcn. + (check_effective_target_vect_pack_trunc): Add amdgcn. + 2020-04-24 Iain Sandoe <iain@sandoe.co.uk> PR c++/94288 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 008def6..f416d5c 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3261,7 +3261,8 @@ proc check_effective_target_vect_cmdline_needed { } { || [check_effective_target_powerpc_altivec])) || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis]) || ([istarget arm*-*-*] && [check_effective_target_arm_neon]) - || [istarget aarch64*-*-*] } { + || [istarget aarch64*-*-*] + || [istarget amdgcn*-*-*]} { return 0 } else { return 1 @@ -6806,7 +6807,8 @@ proc check_effective_target_vect_pack_trunc { } { || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] - && [check_effective_target_s390_vx]) }}] + && [check_effective_target_s390_vx]) + || [istarget amdgcn*-*-*] }}] } # Return 1 if the target plus current options supports a vector @@ -7231,6 +7233,8 @@ proc available_vector_sizes { } { } } elseif { [istarget sparc*-*-*] } { lappend result 64 + } elseif { [istarget amdgcn*-*-*] } { + lappend result 4096 } else { # The traditional default asumption. lappend result 128 |