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| author | Will Schmidt <will_schmidt@vnet.ibm.com> | 2020-09-21 14:26:43 -0500 |
|---|---|---|
| committer | Will Schmidt <will_schmidt@vnet.ibm.com> | 2020-10-08 10:39:10 -0500 |
| commit | cd23ed8af236db2d28314e0652d04e5a0e1540b6 (patch) | |
| tree | c25ddc90c61428012517bb9790f254a441991c79 | |
| parent | 3e1123e52f8eca2650efa0bc81768792d328961f (diff) | |
| download | gcc-cd23ed8af236db2d28314e0652d04e5a0e1540b6.zip gcc-cd23ed8af236db2d28314e0652d04e5a0e1540b6.tar.gz gcc-cd23ed8af236db2d28314e0652d04e5a0e1540b6.tar.bz2 | |
[PATCH, rs6000] Rename BU_P10_MISC_2 define to BU_P10_POWERPC64_MISC_2
Rename our BU_P10_MISC_2 built-in define macro to be
BU_P10_POWERPC64_MISC_2. This more accurately reflects
that the macro includes the RS6000_BTM_POWERPC64 entry,
and matches the style we used for the P7 equivalent.
gcc/ChangeLog:
* config/rs6000/rs6000-builtin.def (BU_P10_MISC_2): Rename
to BU_P10_POWERPC64_MISC_2.
CFUGED, CNTLZDM, CNTTZDM, PDEPD, PEXTD): Call renamed macro.
| -rw-r--r-- | gcc/config/rs6000/rs6000-builtin.def | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index e91a48d..3eb55f0 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1111,7 +1111,7 @@ | RS6000_BTC_UNARY), \ CODE_FOR_ ## ICODE) /* ICODE */ -#define BU_P10_MISC_2(ENUM, NAME, ATTR, ICODE) \ +#define BU_P10_POWERPC64_MISC_2(ENUM, NAME, ATTR, ICODE) \ RS6000_BUILTIN_2 (P10_BUILTIN_ ## ENUM, /* ENUM */ \ "__builtin_" NAME, /* NAME */ \ RS6000_BTM_P10 \ @@ -2727,11 +2727,11 @@ BU_P9_OVERLOAD_2 (CMPRB2, "byte_in_either_range") BU_P9_OVERLOAD_2 (CMPEQB, "byte_in_set") /* Builtins for scalar instructions added in ISA 3.1 (power10). */ -BU_P10_MISC_2 (CFUGED, "cfuged", CONST, cfuged) -BU_P10_MISC_2 (CNTLZDM, "cntlzdm", CONST, cntlzdm) -BU_P10_MISC_2 (CNTTZDM, "cnttzdm", CONST, cnttzdm) -BU_P10_MISC_2 (PDEPD, "pdepd", CONST, pdepd) -BU_P10_MISC_2 (PEXTD, "pextd", CONST, pextd) +BU_P10_POWERPC64_MISC_2 (CFUGED, "cfuged", CONST, cfuged) +BU_P10_POWERPC64_MISC_2 (CNTLZDM, "cntlzdm", CONST, cntlzdm) +BU_P10_POWERPC64_MISC_2 (CNTTZDM, "cnttzdm", CONST, cnttzdm) +BU_P10_POWERPC64_MISC_2 (PDEPD, "pdepd", CONST, pdepd) +BU_P10_POWERPC64_MISC_2 (PEXTD, "pextd", CONST, pextd) /* Builtins for vector instructions added in ISA 3.1 (power10). */ BU_P10V_AV_2 (VCLRLB, "vclrlb", CONST, vclrlb) |