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| author | Uros Bizjak <ubizjak@gmail.com> | 2019-03-10 23:59:31 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2019-03-10 23:59:31 +0100 |
| commit | c89f54838c313ab599fd5c406ebb5c0290aff492 (patch) | |
| tree | 884c38154869edd6d46c39ff21f631d658935d95 | |
| parent | 5f49d2fc4e52398f04a39f81069bb5d1c21bb168 (diff) | |
| download | gcc-c89f54838c313ab599fd5c406ebb5c0290aff492.zip gcc-c89f54838c313ab599fd5c406ebb5c0290aff492.tar.gz gcc-c89f54838c313ab599fd5c406ebb5c0290aff492.tar.bz2 | |
re PR target/68924 (No intrinsic for x86 `MOVQ m64, %xmm` in 32bit mode.)
PR target/68924
* config/i386/sse.md (*vec_extractv2di_0_sse):
Add (=r,x) alternative and corresponding splitter.
From-SVN: r269562
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 30 |
2 files changed, 33 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d1e59d4..24194ab 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-03-10 Uroš Bizjak <ubizjak@gmail.com> + + PR target/68924 + * config/i386/sse.md (*vec_extractv2di_0_sse): + Add (=r,x) alternative and corresponding splitter. + 2019-03-10 Martin Jambor <mjambor@suse.cz> PR tree-optimization/85762 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 259063f..d4c0140 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14308,13 +14308,37 @@ (symbol_ref "true")))]) (define_insn "*vec_extractv2di_0_sse" - [(set (match_operand:DI 0 "nonimmediate_operand" "=v,m") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,x ,m") (vec_select:DI - (match_operand:V2DI 1 "nonimmediate_operand" "vm,v") + (match_operand:V2DI 1 "nonimmediate_operand" " x,xm,x") (parallel [(const_int 0)])))] "TARGET_SSE && !TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))" - "#") + "#" + [(set_attr "isa" "sse4,*,*") + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "0") + (symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC") + ] + (symbol_ref "true")))]) + +(define_split + [(set (match_operand:DI 0 "general_reg_operand") + (vec_select:DI + (match_operand:V2DI 1 "register_operand") + (parallel [(const_int 0)])))] + "TARGET_SSE4_1 && !TARGET_64BIT + && reload_completed" + [(set (match_dup 2) (match_dup 4)) + (set (match_dup 3) + (vec_select:SI + (match_dup 5) + (parallel [(const_int 1)])))] +{ + operands[4] = gen_lowpart (SImode, operands[1]); + operands[5] = gen_lowpart (V4SImode, operands[1]); + split_double_mode (DImode, &operands[0], 1, &operands[2], &operands[3]); +}) (define_split [(set (match_operand:SWI48x 0 "nonimmediate_operand") |