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| author | Uros Bizjak <uros@gcc.gnu.org> | 2015-11-12 09:11:11 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2015-11-12 09:11:11 +0100 |
| commit | c471289ac8af8608dab424693d9411be6042ded6 (patch) | |
| tree | dfcac8342e9525146193da3073ee6dfceaf8eb3f | |
| parent | 61fb1f74fe6402b72c227181833337acc131f205 (diff) | |
| download | gcc-c471289ac8af8608dab424693d9411be6042ded6.zip gcc-c471289ac8af8608dab424693d9411be6042ded6.tar.gz gcc-c471289ac8af8608dab424693d9411be6042ded6.tar.bz2 | |
i386.c (ix86_legitimate_combined_insn): Reject combined insn if the alignment of vector mode memory operand is less...
* config/i386/i386.c (ix86_legitimate_combined_insn): Reject
combined insn if the alignment of vector mode memory operand
is less than ssememalign.
testsuite/ChangeLog:
* gcc.target/i386/sse-1.c (swizzle): Assume that a is
aligned to 64 bits.
From-SVN: r230215
| -rw-r--r-- | gcc/ChangeLog | 16 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 9 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/sse-1.c | 6 |
4 files changed, 25 insertions, 11 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9ab4c6a..815bb08 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,12 +1,18 @@ +2015-11-12 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (ix86_legitimate_combined_insn): Reject + combined insn if the alignment of vector mode memory operand + is less than ssememalign. + 2015-11-12 Tom de Vries <tom@codesourcery.com> - * gen-pass-instances.awk (handle_line): Print parentheses and pass_name - explicitly. + * gen-pass-instances.awk (handle_line): Print parentheses and + pass_name explicitly. 2015-11-12 Tom de Vries <tom@codesourcery.com> - * gen-pass-instances.awk (handle_line): Add pass_num, prefix and postfix - vars. + * gen-pass-instances.awk (handle_line): Add pass_num, prefix + and postfix vars. 2015-11-12 Tom de Vries <tom@codesourcery.com> @@ -45,7 +51,7 @@ Move Convert C1/(X*C2) into (C1/C2)/X to match.pd. Move Optimize (X & (-A)) / A where A is a power of 2, to X >> log2(A) to match.pd. - + * match.pd (rdiv (rdiv:s @0 @1) @2): New simplifier. (rdiv @0 (rdiv:s @1 @2)): New simplifier. (div (convert? (bit_and @0 INTEGER_CST@1)) INTEGER_CST@2): diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index baa0e03..d048b19 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -7236,11 +7236,12 @@ ix86_legitimate_combined_insn (rtx_insn *insn) /* For pre-AVX disallow unaligned loads/stores where the instructions don't support it. */ if (!TARGET_AVX - && VECTOR_MODE_P (GET_MODE (op)) - && misaligned_operand (op, GET_MODE (op))) + && VECTOR_MODE_P (mode) + && misaligned_operand (op, mode)) { - int min_align = get_attr_ssememalign (insn); - if (min_align == 0) + unsigned int min_align = get_attr_ssememalign (insn); + if (min_align == 0 + || MEM_ALIGN (op) < min_align) return false; } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 57384e2..a7326b5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2015-11-12 Uros Bizjak <ubizjak@gmail.com> + + * gcc.target/i386/sse-1.c (swizzle): Assume that a is + aligned to 64 bits. + 2015-11-11 David Edelsohn <dje.gcc@gmail.com> * gcc.dg/pr65521.c: Fail on AIX. diff --git a/gcc/testsuite/gcc.target/i386/sse-1.c b/gcc/testsuite/gcc.target/i386/sse-1.c index afae22d..15d38f9 100644 --- a/gcc/testsuite/gcc.target/i386/sse-1.c +++ b/gcc/testsuite/gcc.target/i386/sse-1.c @@ -14,8 +14,10 @@ typedef union void swizzle (const void *a, vector4_t * b, vector4_t * c) { - b->v = _mm_loadl_pi (b->v, (__m64 *) a); - c->v = _mm_loadl_pi (c->v, ((__m64 *) a) + 1); + __m64 *t = __builtin_assume_aligned (a, 64); + + b->v = _mm_loadl_pi (b->v, t); + c->v = _mm_loadl_pi (c->v, t + 1); } /* While one legal rendering of each statement would be movaps;movlps;movaps, |